From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZEdCp-00070h-Tc for qemu-devel@nongnu.org; Mon, 13 Jul 2015 08:51:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZEdCl-00038k-Qe for qemu-devel@nongnu.org; Mon, 13 Jul 2015 08:51:35 -0400 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]:35245) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZEdCl-00038g-KH for qemu-devel@nongnu.org; Mon, 13 Jul 2015 08:51:31 -0400 Received: by pdrg1 with SMTP id g1so91904829pdr.2 for ; Mon, 13 Jul 2015 05:51:30 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 13 Jul 2015 22:51:00 +1000 Message-Id: <1436791864-4582-4-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1436791864-4582-1-git-send-email-edgar.iglesias@gmail.com> References: <1436791864-4582-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v6 3/7] target-arm: Rename and move gt_cnt_reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index de9b246..27b1833 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1261,7 +1261,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) } } -static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) +static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); int timeridx = ri->opc1 & 1; @@ -1414,7 +1414,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, - .accessfn = gt_ptimer_access, + .accessfn = gt_ptimer_access, .resetfn = gt_timer_reset, .readfn = gt_tval_read, .writefn = gt_tval_write, }, { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, @@ -1425,7 +1425,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, - .accessfn = gt_vtimer_access, + .accessfn = gt_vtimer_access, .resetfn = gt_timer_reset, .readfn = gt_tval_read, .writefn = gt_tval_write, }, /* The counter itself */ @@ -1437,8 +1437,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn = gt_pct_access, - .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, + .accessfn = gt_pct_access, .readfn = gt_cnt_read, }, { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, @@ -1448,8 +1447,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn = gt_vct_access, - .readfn = gt_virt_cnt_read, .resetfn = gt_cnt_reset, + .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, }, /* Comparison value, indicating when the timer goes off */ { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, -- 1.9.1