[Qemu-devel] TLB, cpu_mmu_index() and load/store vs ifetch

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

Hi Paolo, Alex !

I was looking at the patches for speeding up ppc and was trying to
figure out if we could do things better, and reduce the number of modes
and flushes associated with them. While trying to understand it all, I
found something that might be a problem: How we handle the fact that we
can separately turn on/off translation on ppc for I and D side.

However, unless I missed something, qemu currently uses the same helper
to retrieve the mmu index for load/stores and instruction fetches.

Now, the TLB entry itself has different addresses for code, read and
write so it works. However that means that we have to use modes for
every combination of IR and DR in the MSR, which seems like quite a
waste. IE, ignoring PR and HV we already have 4 modes.

Would it be possible to have the target optionally provide a separate
accessor cpu_mmu_index_code() instead and use it in the few places
that actually try to fetch instructions such as get_page_addr_code() ?

That would allow us in effect to have just a single mode entry for
"real mode" (or two if we add support for HV) and simply point to
it appropriately for data or instructions separately.

Is there any reason why that wouldn't work ? I don't yet pretend to
fully understand that part of qemu/tcg :-) Anything I have overlooked ?
(Before I start hacking ...)

Cheers,
Ben.