From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57898) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKTM-0000TD-50 for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:03:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFKTH-0001KW-RP for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:03:32 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:47954) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFKTH-0001JS-K8 for qemu-devel@nongnu.org; Wed, 15 Jul 2015 07:03:27 -0400 From: Aurelien Jarno Date: Wed, 15 Jul 2015 13:03:19 +0200 Message-Id: <1436958199-5181-10-git-send-email-aurelien@aurel32.net> In-Reply-To: <1436958199-5181-1-git-send-email-aurelien@aurel32.net> References: <1436958199-5181-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH RFC 9/9] tcg: update README about size changing ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Aurelien Jarno , Richard Henderson Cc: Paolo Bonzini Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/README | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/tcg/README b/tcg/README index 61b3899..d8fd17a 100644 --- a/tcg/README +++ b/tcg/README @@ -470,8 +470,19 @@ Floating point operations are not supported in this version. A previous incarnation of the code generator had full support of them, but it is better to concentrate on integer operations first. -On a 64 bit target, no assumption is made in TCG about the storage of -the 32 bit values in 64 bit registers. +On a 64 bit target, the values are transfered between 32 and 64-bit +registers by the mean of the following ops: +- trunc_shr_i64_i32 +- ext_i32_i64 +- extu_i32_i64 + +These ops are all optional in that case they are implemented as mov. +This is to allow some optimizations if the target maintains registers +zero or sign extended. For example a MIPS64 CPU requires that all +32-bit values are stored sign-extended in the registers. This means +the trunc_shr_i64_i32 should sign-extend the value when moving it +from a 64-bit to a 32-bit register. It also means ext_i32_i64 can be +implemented as a simple mov as the value is already sign extended. 4.2) Constraints -- 2.1.4