[Qemu-devel] [PATCH RFC 5/9] tcg/i386: implement ext_i32_i64 and extu_i32_i64 ops

[Aurelien Jarno <aurelien@aurel32.net>]

Implementing them as real ops means they can't be optimized out by
the register allocator or the optimizer.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/i386/tcg-target.c | 5 +++++
 tcg/i386/tcg-target.h | 4 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index ff4d9cf..637b1fb 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -2034,9 +2034,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_bswap64_i64:
         tcg_out_bswap64(s, args[0]);
         break;
+    case INDEX_op_extu_i32_i64:
     case INDEX_op_ext32u_i64:
         tcg_out_ext32u(s, args[0], args[1]);
         break;
+    case INDEX_op_ext_i32_i64:
     case INDEX_op_ext32s_i64:
         tcg_out_ext32s(s, args[0], args[1]);
         break;
@@ -2171,6 +2173,9 @@ static const TCGTargetOpDef x86_op_defs[] = {
     { INDEX_op_ext16u_i64, { "r", "r" } },
     { INDEX_op_ext32u_i64, { "r", "r" } },
 
+    { INDEX_op_ext_i32_i64, { "r", "r" } },
+    { INDEX_op_extu_i32_i64, { "r", "r" } },
+
     { INDEX_op_deposit_i64, { "Q", "0", "Q" } },
     { INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } },
 
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 274c97f..16f3949 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -131,8 +131,8 @@ extern bool have_bmi1;
 
 /* size changing optional ops */
 #define TCG_TARGET_HAS_trunc_shr_i64_i32 0
-#define TCG_TARGET_HAS_ext_i32_i64       0
-#define TCG_TARGET_HAS_extu_i32_i64      0
+#define TCG_TARGET_HAS_ext_i32_i64       1
+#define TCG_TARGET_HAS_extu_i32_i64      1
 
 #endif
 
-- 
2.1.4