From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFeN6-0001eJ-TU for qemu-devel@nongnu.org; Thu, 16 Jul 2015 04:18:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFeN5-000737-U7 for qemu-devel@nongnu.org; Thu, 16 Jul 2015 04:18:24 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:65369) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFeN5-00072x-OL for qemu-devel@nongnu.org; Thu, 16 Jul 2015 04:18:23 -0400 From: Leon Alrae Date: Thu, 16 Jul 2015 09:17:37 +0100 Message-ID: <1437034657-31026-10-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1437034657-31026-1-git-send-email-leon.alrae@imgtec.com> References: <1437034657-31026-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 9/9] target-mips: fix page fault address for LWL/LWR/LDL/LDR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno From: Aurelien Jarno When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU currently reports the aligned address in CP0 BadVAddr, while the Windows NT kernel expects the unaligned address. This patch adds a byte access with the unaligned address at the beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page fault and fill the QEMU TLB. Cc: Leon Alrae Reported-by: Herv=C3=A9 Poussineau Tested-by: Herv=C3=A9 Poussineau Signed-off-by: Aurelien Jarno Signed-off-by: Leon Alrae --- target-mips/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 4a1ffdb..d1de35a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2142,6 +2142,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, break; case OPC_LDL: t1 =3D tcg_temp_new(); + /* Do a byte access to possibly trigger a page + fault with the unaligned address. */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 7); #ifndef TARGET_WORDS_BIGENDIAN tcg_gen_xori_tl(t1, t1, 7); @@ -2163,6 +2166,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, break; case OPC_LDR: t1 =3D tcg_temp_new(); + /* Do a byte access to possibly trigger a page + fault with the unaligned address. */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 7); #ifdef TARGET_WORDS_BIGENDIAN tcg_gen_xori_tl(t1, t1, 7); @@ -2229,6 +2235,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, break; case OPC_LWL: t1 =3D tcg_temp_new(); + /* Do a byte access to possibly trigger a page + fault with the unaligned address. */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 3); #ifndef TARGET_WORDS_BIGENDIAN tcg_gen_xori_tl(t1, t1, 3); @@ -2251,6 +2260,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, break; case OPC_LWR: t1 =3D tcg_temp_new(); + /* Do a byte access to possibly trigger a page + fault with the unaligned address. */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 3); #ifdef TARGET_WORDS_BIGENDIAN tcg_gen_xori_tl(t1, t1, 3); --=20 2.1.0