From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFhhZ-0003ge-TL for qemu-devel@nongnu.org; Thu, 16 Jul 2015 07:51:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFhhY-0002Ks-UV for qemu-devel@nongnu.org; Thu, 16 Jul 2015 07:51:45 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34629) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFhhY-0002Kg-ML for qemu-devel@nongnu.org; Thu, 16 Jul 2015 07:51:44 -0400 From: Peter Maydell Date: Thu, 16 Jul 2015 12:47:28 +0100 Message-Id: <1437047249-2357-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1437047249-2357-1-git-send-email-peter.maydell@linaro.org> References: <1437047249-2357-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/4] hw/arm/virt: Wire up secure timer interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , patches@linaro.org Wire up the secure timer interrupt. Since we've defined that the plain old physical timer is the NS timer, we can drop the now-out-of-date comment about QEMU not having TZ. Use a data-driven loop to wire up the timer interrupts, since we now have four of them and the code is the same for each. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index aab99f7..95b1a9a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -392,20 +392,22 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) for (i = 0; i < smp_cpus; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; - /* physical timer; we wire it up to the non-secure timer's ID, - * since a real A15 always has TrustZone but QEMU doesn't. + int irq; + /* Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs we use for the virt board. */ - qdev_connect_gpio_out(cpudev, 0, - qdev_get_gpio_in(gicdev, - ppibase + ARCH_TIMER_NS_EL1_IRQ)); - /* virtual timer */ - qdev_connect_gpio_out(cpudev, 1, - qdev_get_gpio_in(gicdev, - ppibase + ARCH_TIMER_VIRT_IRQ)); - /* Hypervisor timer. */ - qdev_connect_gpio_out(cpudev, 2, - qdev_get_gpio_in(gicdev, - ppibase + ARCH_TIMER_NS_EL2_IRQ)); + const int timer_irq[] = { + [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, + }; + + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[irq])); + } sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, -- 1.9.1