From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49916) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFpfB-0007cO-Sc for qemu-devel@nongnu.org; Thu, 16 Jul 2015 16:21:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFpfA-0007q6-JS for qemu-devel@nongnu.org; Thu, 16 Jul 2015 16:21:49 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34652) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFpfA-0007lW-CA for qemu-devel@nongnu.org; Thu, 16 Jul 2015 16:21:48 -0400 From: Peter Maydell Date: Thu, 16 Jul 2015 21:11:11 +0100 Message-Id: <1437077473-4532-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1437077473-4532-1-git-send-email-peter.maydell@linaro.org> References: <1437077473-4532-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 4/6] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Peter Crosthwaite , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org If the A9 and A15 CPUs which we're creating the peripherals for have TrustZone (EL3) enabled, then also enable it in the GIC we create. Signed-off-by: Peter Maydell --- hw/cpu/a15mpcore.c | 13 +++++++++++++ hw/cpu/a9mpcore.c | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 49727d0..fd0c46a 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -56,10 +56,23 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) SysBusDevice *busdev; int i; Error *err = NULL; + bool has_el3; + Object *cpuobj; gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + + if (!kvm_irqchip_in_kernel()) { + /* Make the GIC's TZ support match the CPUs. We assume that + * either all the CPUs have TZ, or none do. + */ + cpuobj = OBJECT(qemu_get_cpu(0)); + has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && + object_property_get_bool(cpuobj, "has_el3", &error_abort); + qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + } + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c09358c..7046246 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -49,6 +49,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) *wdtbusdev; Error *err = NULL; int i; + bool has_el3; + Object *cpuobj; scudev = DEVICE(&s->scu); qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); @@ -62,6 +64,15 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + + /* Make the GIC's TZ support match the CPUs. We assume that + * either all the CPUs have TZ, or none do. + */ + cpuobj = OBJECT(qemu_get_cpu(0)); + has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && + object_property_get_bool(cpuobj, "has_el3", &error_abort); + qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); -- 1.9.1