Re: [Qemu-devel] [RFC PATCH 3/4] ppc: Use split I/D mmu modes to avoid flushes on interrupts

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Sun, 2015-07-19 at 13:56 +0200, Paolo Bonzini wrote:
> 
> On 19/07/2015 00:20, Benjamin Herrenschmidt wrote:
> > +     * For BookE, we need in theory 8 MMU modes, which would
> > +     * reduce performance, so instead, we ignore msr_hv and
> > +     * will flush on HV context switches. We *could* improve
> > +     * things a bit if needed by using 4 and 5 as HV and flush
> > +     * only when HV mode changes AS but that complicates things
> > +     * as we would need to remember which is the current AS mode
> > +     * for HV for I and D and split more would be hell.
> > +     *
> 
> 8 MMU modes wouldn't reduce performance, only 9 would:

Ok, I assumed incorrectly that 8 was too much based on your changeset
comment:

<<
At 8k per TLB (for 64-bit host or target), 8 or more modes
    make the TLBs bigger than 64k, and some RISC TCG backends do
    not like that.  On the affected hosts, cut the TLB size in
    half---there is still a measurable speedup on PPC with the
    next patch.
>>

IE, you wrote "8 or more".

I can easily fold back guest vs. HV into BookE, though we don't
generally support BookE HV mode anyway in TCG so there's no big hurry in
doing so (we need to add support for the shadow SPRs and a bunch of
other things for that to work).

Cheers,
Ben.


> #define CPU_TLB_BITS                                             \
>     MIN(8,                                                       \
>         TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS -  \
>         (NB_MMU_MODES <= 1 ? 0 :                                 \
>          NB_MMU_MODES <= 2 ? 1 :                                 \
>          NB_MMU_MODES <= 4 ? 2 :                                 \
>          NB_MMU_MODES <= 8 ? 3 : 4))
> 
> Paolo