From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51587) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZGnRU-0005rO-NG for qemu-devel@nongnu.org; Sun, 19 Jul 2015 08:11:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZGnRT-0007AC-Q5 for qemu-devel@nongnu.org; Sun, 19 Jul 2015 08:11:40 -0400 Message-ID: <1437307890.28088.108.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Sun, 19 Jul 2015 22:11:30 +1000 In-Reply-To: <55AB9068.8050202@redhat.com> References: <1437258018-13982-1-git-send-email-benh@kernel.crashing.org> <1437258018-13982-3-git-send-email-benh@kernel.crashing.org> <55AB9068.8050202@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 3/4] ppc: Use split I/D mmu modes to avoid flushes on interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Sun, 2015-07-19 at 13:56 +0200, Paolo Bonzini wrote: > > On 19/07/2015 00:20, Benjamin Herrenschmidt wrote: > > + * For BookE, we need in theory 8 MMU modes, which would > > + * reduce performance, so instead, we ignore msr_hv and > > + * will flush on HV context switches. We *could* improve > > + * things a bit if needed by using 4 and 5 as HV and flush > > + * only when HV mode changes AS but that complicates things > > + * as we would need to remember which is the current AS mode > > + * for HV for I and D and split more would be hell. > > + * > > 8 MMU modes wouldn't reduce performance, only 9 would: Ok, I assumed incorrectly that 8 was too much based on your changeset comment: << At 8k per TLB (for 64-bit host or target), 8 or more modes make the TLBs bigger than 64k, and some RISC TCG backends do not like that. On the affected hosts, cut the TLB size in half---there is still a measurable speedup on PPC with the next patch. >> IE, you wrote "8 or more". I can easily fold back guest vs. HV into BookE, though we don't generally support BookE HV mode anyway in TCG so there's no big hurry in doing so (we need to add support for the shadow SPRs and a bunch of other things for that to work). Cheers, Ben. > #define CPU_TLB_BITS \ > MIN(8, \ > TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ > (NB_MMU_MODES <= 1 ? 0 : \ > NB_MMU_MODES <= 2 ? 1 : \ > NB_MMU_MODES <= 4 ? 2 : \ > NB_MMU_MODES <= 8 ? 3 : 4)) > > Paolo