From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZHa20-0003Kk-Hq for qemu-devel@nongnu.org; Tue, 21 Jul 2015 12:04:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZHa1u-00033A-0k for qemu-devel@nongnu.org; Tue, 21 Jul 2015 12:04:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55623) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZHa1t-000336-S4 for qemu-devel@nongnu.org; Tue, 21 Jul 2015 12:04:29 -0400 From: =?UTF-8?q?Marc=20Mar=C3=AD?= Date: Tue, 21 Jul 2015 18:03:45 +0200 Message-Id: <1437494626-3773-7-git-send-email-markmb@redhat.com> In-Reply-To: <1437494626-3773-1-git-send-email-markmb@redhat.com> References: <1437494626-3773-1-git-send-email-markmb@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC 6/7] Add offset register to fw_cfg DMA interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Marc=20Mar=C3=AD?= , 'Kevin O'Connor' , Gerd Hoffmann , Stefan Hajnoczi Signed-off-by: Marc Mar=C3=AD --- hw/nvram/fw_cfg.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 83205e0..9a39d45 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -47,8 +47,9 @@ #define FW_CFG_DMA_ADDR_LO 0 #define FW_CFG_DMA_ADDR_HI 4 #define FW_CFG_DMA_LENGTH 8 -#define FW_CFG_DMA_CONTROL 12 -#define FW_CFG_DMA_SIZE 16 +#define FW_CFG_DMA_OFFSET 12 +#define FW_CFG_DMA_CONTROL 16 +#define FW_CFG_DMA_SIZE 20 =20 /* FW_CFG_DMA_CONTROL bits */ #define FW_CFG_DMA_CTL_ERROR 0x01 @@ -78,6 +79,7 @@ struct FWCfgState { dma_addr_t dma_addr; uint32_t dma_len; uint32_t dma_ctl; + uint32_t dma_off; }; =20 struct FWCfgIoState { @@ -338,6 +340,10 @@ static void fw_cfg_dma_transfer(FWCfgState *s) return; } =20 + for (i =3D 0; i < s->dma_off; ++i) { + fw_cfg_read(s); + } + for (i =3D 0; i < len; i++) { ptr[i] =3D fw_cfg_read(s); } @@ -366,6 +372,9 @@ static uint64_t fw_cfg_dma_mem_read(void *opaque, hwa= ddr addr, case FW_CFG_DMA_LENGTH: ret =3D s->dma_len; break; + case FW_CFG_DMA_OFFSET: + ret =3D s->dma_off; + break; case FW_CFG_DMA_CONTROL: ret =3D s->dma_ctl; break; @@ -390,6 +399,9 @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr= addr, case FW_CFG_DMA_LENGTH: s->dma_len =3D value; break; + case FW_CFG_DMA_OFFSET: + s->dma_off =3D value; + break; case FW_CFG_DMA_CONTROL: value &=3D FW_CFG_DMA_CTL_MASK; s->dma_ctl =3D value; @@ -528,6 +540,7 @@ static VMStateDescription vmstate_fw_cfg_dma =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT64(dma_addr, FWCfgState), VMSTATE_UINT32(dma_len, FWCfgState), + VMSTATE_UINT32(dma_off, FWCfgState), VMSTATE_UINT32(dma_ctl, FWCfgState), VMSTATE_END_OF_LIST() }, @@ -791,7 +804,7 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, if (dma_addr && dma_as) { FW_CFG(dev)->dma_as =3D dma_as; FW_CFG(dev)->dma_enabled =3D true; - sysbus_mmio_map(sbd, 1, dma_addr); + sysbus_mmio_map(sbd, 2, dma_addr); } =20 return FW_CFG(dev); --=20 2.4.3