From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46753) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZIenD-0003CE-TL for qemu-devel@nongnu.org; Fri, 24 Jul 2015 11:21:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZIenC-0000i7-SA for qemu-devel@nongnu.org; Fri, 24 Jul 2015 11:21:47 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZIenC-0000hC-I6 for qemu-devel@nongnu.org; Fri, 24 Jul 2015 11:21:46 -0400 From: Peter Maydell Date: Fri, 24 Jul 2015 16:20:59 +0100 Message-Id: <1437751263-21913-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1437751263-21913-1-git-send-email-peter.maydell@linaro.org> References: <1437751263-21913-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 1/5] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , patches@linaro.org For EL2 stage 1 translations, there is no TTBR1. We were already handling this for 64-bit EL2; add the code to take the 'no TTBR1' code path for 64-bit EL2 as well. Signed-off-by: Peter Maydell --- target-arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 01f0d0d..1ac6594 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5638,6 +5638,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (el > 1) { ttbr1_valid = false; } + } else { + /* There is no TTBR1 for EL2 */ + if (el == 2) { + ttbr1_valid = false; + } } /* Determine whether this address is in the region controlled by -- 1.9.1