From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZIenD-0003Bn-Kz for qemu-devel@nongnu.org; Fri, 24 Jul 2015 11:21:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZIenC-0000hj-4b for qemu-devel@nongnu.org; Fri, 24 Jul 2015 11:21:47 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZIenB-0000hC-Th for qemu-devel@nongnu.org; Fri, 24 Jul 2015 11:21:46 -0400 From: Peter Maydell Date: Fri, 24 Jul 2015 16:21:03 +0100 Message-Id: <1437751263-21913-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1437751263-21913-1-git-send-email-peter.maydell@linaro.org> References: <1437751263-21913-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 5/5] target-arm: Implement AArch32 ATS1H* operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , patches@linaro.org Implement the AArch32 ATS1H* operations which perform Hyp mode stage 1 translations. Signed-off-by: Peter Maydell --- target-arm/helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 67d108e..b9ce965 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1607,6 +1607,17 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) A32_BANKED_CURRENT_REG_SET(env, par, par64); } +static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int access_type = ri->opc2 & 1; + uint64_t par64; + + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri) { if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { @@ -2770,6 +2781,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, .accessfn = at_s1e2_access, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 + * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose + * to behave as if SCR.NS was 1. + */ + { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, + .access = PL2_W, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, + { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, + .access = PL2_W, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, #endif REGINFO_SENTINEL }; -- 1.9.1