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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, patches@linaro.org
Subject: [Qemu-devel] [PATCH 1/5] armv7m_nvic: Implement ICSR without using internal GIC state
Date: Tue, 28 Jul 2015 14:22:24 +0100	[thread overview]
Message-ID: <1438089748-5528-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1438089748-5528-1-git-send-email-peter.maydell@linaro.org>

Change the implementation of the Interrupt Control and State Register
in the v7M NVIC to not use the running_irq and last_active internal
state fields in the GIC. These fields don't correspond to state in
a real GIC and will be removed soon.
The changes to the ICSR are:
 * the VECTACTIVE field is documented as identical to the IPSR[8:0]
   field, so implement it that way
 * implement RETTOBASE via looking at the active state bits

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/armv7m_nvic.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index e13b729..3ec8408 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -185,26 +185,25 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
         return cpu->midr;
     case 0xd04: /* Interrupt Control State.  */
         /* VECTACTIVE */
-        val = s->gic.running_irq[0];
+        cpu = ARM_CPU(current_cpu);
+        val = cpu->env.v7m.exception;
         if (val == 1023) {
             val = 0;
         } else if (val >= 32) {
             val -= 16;
         }
-        /* RETTOBASE */
-        if (s->gic.running_irq[0] == 1023
-                || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
-            val |= (1 << 11);
-        }
         /* VECTPENDING */
         if (s->gic.current_pending[0] != 1023)
             val |= (s->gic.current_pending[0] << 12);
-        /* ISRPENDING */
+        /* ISRPENDING and RETTOBASE */
         for (irq = 32; irq < s->num_irq; irq++) {
             if (s->gic.irq_state[irq].pending) {
                 val |= (1 << 22);
                 break;
             }
+            if (irq != cpu->env.v7m.exception && s->gic.irq_state[irq].active) {
+                val |= (1 << 11);
+            }
         }
         /* PENDSTSET */
         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
-- 
1.9.1

  reply	other threads:[~2015-07-28 13:22 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-28 13:22 [Qemu-devel] [PATCH 0/5] arm_gic: Drop running_irq and last_active arrays Peter Maydell
2015-07-28 13:22 ` Peter Maydell [this message]
2015-07-28 13:22 ` [Qemu-devel] [PATCH 2/5] hw/intc/arm_gic: Running priority is group priority, not full priority Peter Maydell
2015-07-28 13:22 ` [Qemu-devel] [PATCH 3/5] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers Peter Maydell
2015-07-28 13:22 ` [Qemu-devel] [PATCH 4/5] hw/intc/arm_gic: Drop running_irq and last_active arrays Peter Maydell
2015-07-28 13:22 ` [Qemu-devel] [PATCH 5/5] hw/intc/arm_gic: Actually set the active bits for active interrupts Peter Maydell
2015-08-14 10:11 ` [Qemu-devel] [PATCH 0/5] arm_gic: Drop running_irq and last_active arrays Peter Maydell
2015-09-07 12:00   ` Peter Maydell

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