From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36009) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZLCdp-0000z6-7L for qemu-devel@nongnu.org; Fri, 31 Jul 2015 11:54:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZLCdg-0005uB-J3 for qemu-devel@nongnu.org; Fri, 31 Jul 2015 11:54:37 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:37257) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZLCdg-0005u5-Dt for qemu-devel@nongnu.org; Fri, 31 Jul 2015 11:54:28 -0400 Received: by wibud3 with SMTP id ud3so37563675wib.0 for ; Fri, 31 Jul 2015 08:54:27 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Fri, 31 Jul 2015 16:53:56 +0100 Message-Id: <1438358041-18021-7-git-send-email-alex.bennee@linaro.org> In-Reply-To: <1438358041-18021-1-git-send-email-alex.bennee@linaro.org> References: <1438358041-18021-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [kvm-unit-tests PATCH v5 06/11] lib/arm: add flush_tlb_page mmu function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mttcg@listserver.greensocs.com, mark.burton@greensocs.com, fred.konrad@greensocs.com Cc: peter.maydell@linaro.org, drjones@redhat.com, kvm@vger.kernel.org, a.spyridakis@virtualopensystems.com, claudio.fontana@huawei.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= This introduces a new flush_tlb_page function which does exactly what you expect. It's going to be useful for the future TLB torture test. Signed-off-by: Alex Bennée --- lib/arm/asm/mmu.h | 11 +++++++++++ lib/arm64/asm/mmu.h | 8 ++++++++ 2 files changed, 19 insertions(+) diff --git a/lib/arm/asm/mmu.h b/lib/arm/asm/mmu.h index c1bd01c..2bb0cde 100644 --- a/lib/arm/asm/mmu.h +++ b/lib/arm/asm/mmu.h @@ -14,8 +14,11 @@ #define PTE_AF PTE_EXT_AF #define PTE_WBWA L_PTE_MT_WRITEALLOC +/* See B3.18.7 TLB maintenance operations */ + static inline void local_flush_tlb_all(void) { + /* TLBIALL */ asm volatile("mcr p15, 0, %0, c8, c7, 0" :: "r" (0)); dsb(); isb(); @@ -27,6 +30,14 @@ static inline void flush_tlb_all(void) local_flush_tlb_all(); } +static inline void flush_tlb_page(unsigned long vaddr) +{ + /* TLBIMVAA */ + asm volatile("mcr p15, 0, %0, c8, c7, 3" :: "r" (vaddr)); + dsb(); + isb(); +} + #include #endif /* __ASMARM_MMU_H_ */ diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h index 18b4d6b..3bc31c9 100644 --- a/lib/arm64/asm/mmu.h +++ b/lib/arm64/asm/mmu.h @@ -19,6 +19,14 @@ static inline void flush_tlb_all(void) isb(); } +static inline void flush_tlb_page(unsigned long vaddr) +{ + unsigned long page = vaddr >> 12; + dsb(ishst); + asm("tlbi vaae1is, %0" :: "r" (page)); + dsb(ish); +} + #include #endif /* __ASMARM64_MMU_H_ */ -- 2.5.0