From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44091) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZNIvp-0003AH-VT for qemu-devel@nongnu.org; Thu, 06 Aug 2015 07:01:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZNIvn-0006QS-U3 for qemu-devel@nongnu.org; Thu, 06 Aug 2015 07:01:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47182) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZNIvn-0006QJ-L9 for qemu-devel@nongnu.org; Thu, 06 Aug 2015 07:01:51 -0400 From: =?UTF-8?q?Marc=20Mar=C3=AD?= Date: Thu, 6 Aug 2015 13:01:16 +0200 Message-Id: <1438858878-29450-4-git-send-email-markmb@redhat.com> In-Reply-To: <1438858878-29450-1-git-send-email-markmb@redhat.com> References: <1438858816-29385-1-git-send-email-markmb@redhat.com> <1438858878-29450-1-git-send-email-markmb@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 3/5] Implement fw_cfg DMA interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Drew , Stefan Hajnoczi , Kevin O'Connor , Gerd Hoffmann , =?UTF-8?q?Marc=20Mar=C3=AD?= , Laszlo Based on the specifications on docs/specs/fw_cfg.txt This interface is an addon. The old interface can still be used as usual. For x86 arch, this addon will use one extra port (0x512). For ARM, it wil= l use 8 more bytes, following the actual implementation. Based on Gerd Hoffman's initial implementation. Signed-off-by: Marc Mar=C3=AD --- hw/arm/virt.c | 2 +- hw/nvram/fw_cfg.c | 212 ++++++++++++++++++++++++++++++++++++++++= +++--- include/hw/nvram/fw_cfg.h | 12 ++- 3 files changed, 211 insertions(+), 15 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4846892..374660c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -612,7 +612,7 @@ static void create_fw_cfg(const VirtBoardInfo *vbi) hwaddr size =3D vbi->memmap[VIRT_FW_CFG].size; char *nodename; =20 - fw_cfg_init_mem_wide(base + 8, base, 8); + fw_cfg_init_mem_wide(base + 8, base, 8, 0, NULL); =20 nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base); qemu_fdt_add_subnode(vbi->fdt, nodename); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 88481b7..7399008 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -23,6 +23,7 @@ */ #include "hw/hw.h" #include "sysemu/sysemu.h" +#include "sysemu/dma.h" #include "hw/isa/isa.h" #include "hw/nvram/fw_cfg.h" #include "hw/sysbus.h" @@ -30,10 +31,13 @@ #include "qemu/error-report.h" #include "qemu/config-file.h" =20 -#define FW_CFG_SIZE 2 +#define FW_CFG_SIZE 3 #define FW_CFG_NAME "fw_cfg" #define FW_CFG_PATH "/machine/" FW_CFG_NAME =20 +#define FW_CFG_VERSION 1 +#define FW_CFG_VERSION_DMA 2 + #define TYPE_FW_CFG "fw_cfg" #define TYPE_FW_CFG_IO "fw_cfg_io" #define TYPE_FW_CFG_MEM "fw_cfg_mem" @@ -42,6 +46,11 @@ #define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_I= O) #define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_M= EM) =20 +/* FW_CFG_DMA_CONTROL bits */ +#define FW_CFG_DMA_CTL_ERROR 0x01 +#define FW_CFG_DMA_CTL_READ 0x02 +#define FW_CFG_DMA_CTL_MASK 0x03 + typedef struct FWCfgEntry { uint32_t len; uint8_t *data; @@ -59,6 +68,10 @@ struct FWCfgState { uint16_t cur_entry; uint32_t cur_offset; Notifier machine_ready; + + bool dma_enabled; + AddressSpace *dma_as; + dma_addr_t dma_addr; }; =20 struct FWCfgIoState { @@ -75,7 +88,7 @@ struct FWCfgMemState { FWCfgState parent_obj; /*< public >*/ =20 - MemoryRegion ctl_iomem, data_iomem; + MemoryRegion ctl_iomem, data_iomem, dma_iomem; uint32_t data_width; MemoryRegionOps wide_data_ops; }; @@ -294,6 +307,108 @@ static void fw_cfg_data_mem_write(void *opaque, hwa= ddr addr, } while (i); } =20 +static void fw_cfg_dma_transfer(FWCfgState *s) +{ + dma_addr_t len; + uint8_t *ptr; + FWCfgDmaAccess *dma; + int arch =3D !!(s->cur_entry & FW_CFG_ARCH_LOCAL); + FWCfgEntry *e =3D &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK= ]; + + len =3D sizeof(*dma); + dma =3D dma_memory_map(s->dma_as, s->dma_addr, &len, + DMA_DIRECTION_FROM_DEVICE); + + if (!dma || !len) { + return; + } + + if (dma->control & FW_CFG_DMA_CTL_ERROR) { + return; + } + + if (!(dma->control & FW_CFG_DMA_CTL_READ)) { + return; + } + + while (dma->length > 0) { + if (s->cur_entry =3D=3D FW_CFG_INVALID || !e->data || + s->cur_offset >=3D e->len) { + len =3D dma->length; + if (dma->address) { + ptr =3D dma_memory_map(s->dma_as, dma->address, &len, + DMA_DIRECTION_FROM_DEVICE); + if (!ptr || !len) { + dma->control |=3D FW_CFG_DMA_CTL_ERROR; + goto out; + } + + memset(ptr, 0, len); + + dma_memory_unmap(s->dma_as, ptr, len, + DMA_DIRECTION_FROM_DEVICE, len); + } + + dma->address +=3D len; + dma->length -=3D len; + } else { + if (dma->length <=3D e->len) { + len =3D dma->length; + } else { + len =3D e->len; + } + + if (e->read_callback) { + e->read_callback(e->callback_opaque, s->cur_offset); + } + + if (dma->address) { + ptr =3D dma_memory_map(s->dma_as, dma->address, &len, + DMA_DIRECTION_FROM_DEVICE); + if (!ptr || !len) { + dma->control |=3D FW_CFG_DMA_CTL_ERROR; + goto out; + } + + memcpy(ptr, &e->data[s->cur_offset], len); + + dma_memory_unmap(s->dma_as, ptr, len, + DMA_DIRECTION_FROM_DEVICE, len); + } + + s->cur_offset +=3D len; + + dma->address +=3D len; + dma->length -=3D len; + + dma->control =3D 0; + } + } + + trace_fw_cfg_read(s, 0); + +out: + dma_memory_unmap(s->dma_as, dma, sizeof(*dma), + DMA_DIRECTION_FROM_DEVICE, sizeof(*dma))= ; + return; + +} + +static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + FWCfgState *s =3D opaque; + + s->dma_addr =3D be64_to_cpu(value); + fw_cfg_dma_transfer(s); +} + +static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + return is_write && addr =3D=3D 0; +} + static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, unsigned size, bool is_write) { @@ -321,12 +436,20 @@ static uint64_t fw_cfg_comb_read(void *opaque, hwad= dr addr, static void fw_cfg_comb_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - switch (size) { + FWCfgState *s; + + switch (addr) { + case 0: + fw_cfg_select(opaque, (uint16_t)value); + break; case 1: fw_cfg_write(opaque, (uint8_t)value); break; case 2: - fw_cfg_select(opaque, (uint16_t)value); + /* FWCfgDmaAccess address */ + s =3D opaque; + s->dma_addr =3D le64_to_cpu(value); + fw_cfg_dma_transfer(s); break; } } @@ -334,7 +457,11 @@ static void fw_cfg_comb_write(void *opaque, hwaddr a= ddr, static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, unsigned size, bool is_write) { - return (size =3D=3D 1) || (is_write && size =3D=3D 2); + FWCfgState *s =3D opaque; + + return (is_write && size =3D=3D 2 && addr =3D=3D 0) || + (size =3D=3D 1 && addr =3D=3D 1) || + (s->dma_enabled && is_write && addr =3D=3D 2); } =20 static const MemoryRegionOps fw_cfg_ctl_mem_ops =3D { @@ -361,6 +488,12 @@ static const MemoryRegionOps fw_cfg_comb_mem_ops =3D= { .valid.accepts =3D fw_cfg_comb_valid, }; =20 +static const MemoryRegionOps fw_cfg_dma_mem_ops =3D { + .write =3D fw_cfg_dma_mem_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid.accepts =3D fw_cfg_dma_mem_valid, +}; + static void fw_cfg_reset(DeviceState *d) { FWCfgState *s =3D FW_CFG(d); @@ -401,6 +534,22 @@ static bool is_version_1(void *opaque, int version_i= d) return version_id =3D=3D 1; } =20 +static bool fw_cfg_dma_enabled(void *opaque) +{ + FWCfgState *s =3D opaque; + + return s->dma_enabled; +} + +static VMStateDescription vmstate_fw_cfg_dma =3D { + .name =3D "fw_cfg/dma", + .needed =3D fw_cfg_dma_enabled, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(dma_addr, FWCfgState), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_fw_cfg =3D { .name =3D "fw_cfg", .version_id =3D 2, @@ -410,6 +559,10 @@ static const VMStateDescription vmstate_fw_cfg =3D { VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_fw_cfg_dma, + NULL, } }; =20 @@ -595,7 +748,6 @@ static void fw_cfg_init1(DeviceState *dev) qdev_init_nofail(dev); =20 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); - fw_cfg_add_i32(s, FW_CFG_ID, 1); fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16); fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type =3D=3D D= T_NOGRAPHIC)); fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); @@ -607,22 +759,42 @@ static void fw_cfg_init1(DeviceState *dev) qemu_add_machine_init_done_notifier(&s->machine_ready); } =20 -FWCfgState *fw_cfg_init_io(uint32_t iobase) +FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, AddressSpace *dma_as) { DeviceState *dev; + FWCfgState *s; =20 dev =3D qdev_create(NULL, TYPE_FW_CFG_IO); qdev_prop_set_uint32(dev, "iobase", iobase); + + s =3D FW_CFG(dev); fw_cfg_init1(dev); =20 - return FW_CFG(dev); + if (dma_as) { + /* 64 bits for the address field */ + s->dma_as =3D dma_as; + s->dma_enabled =3D true; + + fw_cfg_add_i32(s, FW_CFG_ID, FW_CFG_VERSION_DMA); + } else { + fw_cfg_add_i32(s, FW_CFG_ID, FW_CFG_VERSION); + } + + return s; } =20 -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr, - uint32_t data_width) +FWCfgState *fw_cfg_init_io(uint32_t iobase) +{ + return fw_cfg_init_io_dma(iobase, NULL); +} + +FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as) { DeviceState *dev; SysBusDevice *sbd; + FWCfgState *s; =20 dev =3D qdev_create(NULL, TYPE_FW_CFG_MEM); qdev_prop_set_uint32(dev, "data_width", data_width); @@ -633,13 +805,25 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, h= waddr data_addr, sysbus_mmio_map(sbd, 0, ctl_addr); sysbus_mmio_map(sbd, 1, data_addr); =20 - return FW_CFG(dev); + s =3D FW_CFG(dev); + + if (dma_addr && dma_as) { + s->dma_as =3D dma_as; + s->dma_enabled =3D true; + sysbus_mmio_map(sbd, 2, dma_addr); + fw_cfg_add_i32(s, FW_CFG_ID, FW_CFG_VERSION_DMA); + } else { + fw_cfg_add_i32(s, FW_CFG_ID, FW_CFG_VERSION); + } + + return s; } =20 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) { return fw_cfg_init_mem_wide(ctl_addr, data_addr, - fw_cfg_data_mem_ops.valid.max_access_siz= e); + fw_cfg_data_mem_ops.valid.max_access_siz= e, + 0, NULL); } =20 =20 @@ -725,6 +909,10 @@ static void fw_cfg_mem_realize(DeviceState *dev, Err= or **errp) memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s)= , "fwcfg.data", data_ops->valid.max_access_size)= ; sysbus_init_mmio(sbd, &s->data_iomem); + + memory_region_init_io(&s->dma_iomem, OBJECT(s), &fw_cfg_dma_mem_ops, + FW_CFG(s), "fwcfg.dma", sizeof(dma_addr_t)); + sysbus_init_mmio(sbd, &s->dma_iomem); } =20 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index e60d3ca..4ce51e2 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -61,6 +61,12 @@ typedef struct FWCfgFiles { FWCfgFile f[]; } FWCfgFiles; =20 +typedef struct FWCfgDmaAccess { + uint64_t address; + uint32_t length; + uint32_t control; +} FWCfgDmaAccess; + typedef void (*FWCfgCallback)(void *opaque, uint8_t *data); typedef void (*FWCfgReadCallback)(void *opaque, uint32_t offset); =20 @@ -77,10 +83,12 @@ void fw_cfg_add_file_callback(FWCfgState *s, const ch= ar *filename, void *data, size_t len); void *fw_cfg_modify_file(FWCfgState *s, const char *filename, void *data= , size_t len); +FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_io(uint32_t iobase); FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr); -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr, - uint32_t data_width); +FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as); =20 FWCfgState *fw_cfg_find(void); =20 --=20 2.4.3