From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36091) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPq0P-0005TV-9h for qemu-devel@nongnu.org; Thu, 13 Aug 2015 06:45:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZPq0M-0005Qv-Ut for qemu-devel@nongnu.org; Thu, 13 Aug 2015 06:45:05 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34909) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPq0M-0005DT-MZ for qemu-devel@nongnu.org; Thu, 13 Aug 2015 06:45:02 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZPq08-000724-Eq for qemu-devel@nongnu.org; Thu, 13 Aug 2015 11:44:48 +0100 From: Peter Maydell Date: Thu, 13 Aug 2015 11:44:46 +0100 Message-Id: <1439462687-26903-27-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1439462687-26903-1-git-send-email-peter.maydell@linaro.org> References: <1439462687-26903-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Since we now support both the hypervisor and the secure physical timer, wire their interrupt lines up in the a15mpcore wrapper object. Signed-off-by: Peter Maydell Message-id: 1437047249-2357-5-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias --- hw/cpu/a15mpcore.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index e31a1f9..58ac02e 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -75,14 +75,21 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) for (i = 0; i < s->num_cpu; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); int ppibase = s->num_irq - 32 + i * 32; - /* physical timer; we wire it up to the non-secure timer's ID, - * since a real A15 always has TrustZone but QEMU doesn't. + int irq; + /* Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used on the A15: */ - qdev_connect_gpio_out(cpudev, 0, - qdev_get_gpio_in(gicdev, ppibase + 30)); - /* virtual timer */ - qdev_connect_gpio_out(cpudev, 1, - qdev_get_gpio_in(gicdev, ppibase + 27)); + const int timer_irq[] = { + [GTIMER_PHYS] = 30, + [GTIMER_VIRT] = 27, + [GTIMER_HYP] = 26, + [GTIMER_SEC] = 29, + }; + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[irq])); + } } /* Memory map (addresses are offsets from PERIPHBASE): -- 1.9.1