From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35397) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPrPJ-0008O7-CA for qemu-devel@nongnu.org; Thu, 13 Aug 2015 08:14:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZPrPF-0007ds-1u for qemu-devel@nongnu.org; Thu, 13 Aug 2015 08:14:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPrPE-0007dh-R5 for qemu-devel@nongnu.org; Thu, 13 Aug 2015 08:14:48 -0400 Date: Thu, 13 Aug 2015 15:14:45 +0300 From: "Michael S. Tsirkin" Message-ID: <1439468033-6413-4-git-send-email-mst@redhat.com> References: <1439468033-6413-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1439468033-6413-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 03/24] piix: Document coreboot-specific RAM size config register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Ed Swierk , Eduardo Habkost , Richard Smith From: Eduardo Habkost The existing i440fx initialization code sets a PCI config register that isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is DRAMC (DRAM Control) and has nothing to do with the RAM size. This was implemented in commit ec5f92ce6ac8ec09056be77e03c941be188648fa because old coreboot code tried to read registers 0x5a-0x5f,0x56,0x57 to get the RAM size from QEMU, but I couldn't find out why coreboot did that. I assume it was a mistake, and the original code was supposed to be reading the DRB[0-7] registers (offsets 0x60-0x67). Document that coreboot-specific register offset in a macro and a comment, for future reference. Cc: Ed Swierk Cc: Richard Smith Signed-off-by: Eduardo Habkost Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/pci-host/piix.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index ad55f99..1cb25f3 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -117,6 +117,11 @@ struct PCII440FXState { #define I440FX_PAM_SIZE 7 #define I440FX_SMRAM 0x72 +/* Older coreboot versions (4.0 and older) read a config register that doesn't + * exist in real hardware, to get the RAM size from QEMU. + */ +#define I440FX_COREBOOT_RAM_SIZE 0x57 + static void piix3_set_irq(void *opaque, int pirq, int level); static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); static void piix3_write_config_xen(PCIDevice *dev, @@ -394,7 +399,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, if (ram_size > 255) { ram_size = 255; } - d->config[0x57] = ram_size; + d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; i440fx_update_memory_mappings(f); -- MST