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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: Christopher Covington <christopher.covington@linaro.org>,
	patches@linaro.org
Subject: [Qemu-devel] [PATCH 7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
Date: Thu, 13 Aug 2015 17:35:43 +0100	[thread overview]
Message-ID: <1439483745-28752-8-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1439483745-28752-1-git-send-email-peter.maydell@linaro.org>

The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/arm-semi.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 1d4cc59..1d0d7aa 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -58,6 +58,7 @@
 #define TARGET_SYS_GET_CMDLINE 0x15
 #define TARGET_SYS_HEAPINFO    0x16
 #define TARGET_SYS_EXIT        0x18
+#define TARGET_SYS_SYNCCACHE   0x19
 
 /* ADP_Stopped_ApplicationExit is used for exit(0),
  * anything else is implemented as exit(1) */
@@ -623,6 +624,15 @@ target_ulong do_arm_semihosting(CPUARMState *env)
         ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
         gdb_exit(env, ret);
         exit(ret);
+    case TARGET_SYS_SYNCCACHE:
+        /* Clean the D-cache and invalidate the I-cache for the specified
+         * virtual address range. This is a nop for us since we don't
+         * implement caches. This is only present on A64.
+         */
+        if (is_a64(env)) {
+            return 0;
+        }
+        /* fall through -- invalid for A32/T32 */
     default:
         fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
         cpu_dump_state(cs, stderr, fprintf, 0);
-- 
1.9.1

  parent reply	other threads:[~2015-08-13 16:51 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-13 16:35 [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting Peter Maydell
2015-08-13 16:35 ` [Qemu-devel] [PATCH 1/9] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb Peter Maydell
2015-08-13 16:35 ` [Qemu-devel] [PATCH 2/9] target-arm: Improve semihosting debug prints Peter Maydell
2015-08-13 16:35 ` [Qemu-devel] [PATCH 3/9] gdbstub: Implement gdb_do_syscallv() Peter Maydell
2015-08-13 16:35 ` [Qemu-devel] [PATCH 4/9] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' Peter Maydell
2015-08-19 15:52   ` Christopher Covington
2015-08-13 16:35 ` [Qemu-devel] [PATCH 5/9] include/exec/softmmu-semi.h: Add support for 64-bit values Peter Maydell
2015-08-13 16:35 ` [Qemu-devel] [PATCH 6/9] target-arm/arm-semi.c: Support widening APIs to 64 bits Peter Maydell
2015-08-19 20:59   ` Christopher Covington
2015-08-13 16:35 ` Peter Maydell [this message]
2015-08-19 21:01   ` [Qemu-devel] [PATCH 7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call Christopher Covington
2015-08-13 16:35 ` [Qemu-devel] [PATCH 8/9] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block Peter Maydell
2015-08-13 16:35 ` [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction Peter Maydell
2015-08-19 16:19   ` Christopher Covington
2015-08-27 18:35   ` Peter Maydell
2015-09-14 18:36     ` Christopher Covington
2015-08-25 20:40 ` [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting Christopher Covington

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