From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35067) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQCaY-0004z6-Bz for qemu-devel@nongnu.org; Fri, 14 Aug 2015 06:51:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZQCaX-0002w8-Ey for qemu-devel@nongnu.org; Fri, 14 Aug 2015 06:51:54 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34941) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQCaX-0002u4-8H for qemu-devel@nongnu.org; Fri, 14 Aug 2015 06:51:53 -0400 From: Peter Maydell Date: Fri, 14 Aug 2015 11:41:17 +0100 Message-Id: <1439548879-1972-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1439548879-1972-1-git-send-email-peter.maydell@linaro.org> References: <1439548879-1972-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 4/6] target-arm: Implement missing EL2 TLBI operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Implement the missing TLBI operations that exist only if EL2 is implemented. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index aea8b33..77ce718 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2562,6 +2562,16 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); + } +} + static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3065,10 +3075,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, .type = ARM_CP_NO_RAW, .access = PL2_W, .writefn = tlbi_aa64_vae2_write }, + { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_vae2_write }, + { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_alle2is_write }, { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, .type = ARM_CP_NO_RAW, .access = PL2_W, .writefn = tlbi_aa64_vae2is_write }, + { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, -- 1.9.1