From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQGSq-0007kU-QH for qemu-devel@nongnu.org; Fri, 14 Aug 2015 11:00:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZQGSp-0006c0-RA for qemu-devel@nongnu.org; Fri, 14 Aug 2015 11:00:12 -0400 Received: from mail-qk0-x22e.google.com ([2607:f8b0:400d:c09::22e]:34748) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZQGSp-0006bd-Nd for qemu-devel@nongnu.org; Fri, 14 Aug 2015 11:00:11 -0400 Received: by qkcs67 with SMTP id s67so26427653qkc.1 for ; Fri, 14 Aug 2015 08:00:11 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 14 Aug 2015 07:59:22 -0700 Message-Id: <1439564366-11633-8-git-send-email-rth@twiddle.net> In-Reply-To: <1439564366-11633-1-git-send-email-rth@twiddle.net> References: <1439564366-11633-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 07/11] target-m68k: Use setcond for scc List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, schwab@linux-m68k.org, laurent@vivier.eu, gerg@uclinux.org Signed-off-by: Richard Henderson --- target-m68k/translate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index ce48e2a..28c3e1e 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -886,19 +886,21 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) DISAS_INSN(scc) { - TCGLabel *l1; + DisasCompare c; int cond; - TCGv reg; + TCGv reg, tmp; - l1 = gen_new_label(); cond = (insn >> 8) & 0xf; + gen_cc_cond(&c, s, cond); + + tmp = tcg_temp_new(); + tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); + free_cond(&c); + reg = DREG(insn, 0); - tcg_gen_andi_i32(reg, reg, 0xffffff00); - /* This is safe because we modify the reg directly, with no other values - live. */ - gen_jmpcc(s, cond ^ 1, l1); - tcg_gen_ori_i32(reg, reg, 0xff); - gen_set_label(l1); + tcg_gen_neg_i32(tmp, tmp); + tcg_gen_deposit_i32(reg, reg, tmp, 0, 8); + tcg_temp_free(tmp); } /* Force a TB lookup after an instruction that changes the CPU state. */ -- 2.4.3