From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRQG0-00066L-Bq for qemu-devel@nongnu.org; Mon, 17 Aug 2015 15:39:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZRQFx-0008KR-GA for qemu-devel@nongnu.org; Mon, 17 Aug 2015 15:39:44 -0400 Received: from mail-qg0-x233.google.com ([2607:f8b0:400d:c04::233]:36600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRQFx-0008KL-Bw for qemu-devel@nongnu.org; Mon, 17 Aug 2015 15:39:41 -0400 Received: by qgdd90 with SMTP id d90so101565346qgd.3 for ; Mon, 17 Aug 2015 12:39:41 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Aug 2015 12:38:34 -0700 Message-Id: <1439840320-20897-12-git-send-email-rth@twiddle.net> In-Reply-To: <1439840320-20897-1-git-send-email-rth@twiddle.net> References: <1439840320-20897-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 11/17] tcg: update README about size changing ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Aurelien Jarno From: Aurelien Jarno Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/README | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/README b/tcg/README index 61b3899..a22f251 100644 --- a/tcg/README +++ b/tcg/README @@ -466,13 +466,25 @@ On a 32 bit target, all 64 bit operations are converted to 32 bits. A few specific operations must be implemented to allow it (see add2_i32, sub2_i32, brcond2_i32). +On a 64 bit target, the values are transfered between 32 and 64-bit +registers using the following ops: +- trunc_shr_i64_i32 +- ext_i32_i64 +- extu_i32_i64 + +They ensure that the values are correctly truncated or extended when +moved from a 32-bit to a 64-bit register or vice-versa. Note that the +trunc_shr_i64_i32 is an optional op. It is not necessary to implement +it if all the following conditions are met: +- 64-bit registers can hold 32-bit values +- 32-bit values in a 64-bit register do not need to stay zero or + sign extended +- all 32-bit TCG ops ignore the high part of 64-bit registers + Floating point operations are not supported in this version. A previous incarnation of the code generator had full support of them, but it is better to concentrate on integer operations first. -On a 64 bit target, no assumption is made in TCG about the storage of -the 32 bit values in 64 bit registers. - 4.2) Constraints GCC like constraints are used to define the constraints of every -- 2.4.3