From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTAmh-0008UC-Ev for qemu-devel@nongnu.org; Sat, 22 Aug 2015 11:32:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZTAmg-0003T5-F8 for qemu-devel@nongnu.org; Sat, 22 Aug 2015 11:32:43 -0400 From: Cormac O'Brien Date: Sat, 22 Aug 2015 10:32:10 -0500 Message-Id: <1440257533-1504-2-git-send-email-cormac@c-obrien.org> In-Reply-To: <1440257533-1504-1-git-send-email-cormac@c-obrien.org> References: <1440257533-1504-1-git-send-email-cormac@c-obrien.org> Subject: [Qemu-devel] [PATCH 1/4] PPC: Allow Rc bit to be set on mtspr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: agraf@suse.de, mark.cave-ayland@ilande.co.uk, qemu-devel@nongnu.org, qemu-ppc@nongnu.org From: Alexander Graf According to the ISA setting the Rc bit on mtspr is undefined behavior. Real 750 hardware simply ignores the bit and doesn't touch cr0 though. Unfortunately, Mac OS 9 relies on this fact and executes a few mtspr instructions (to set XER for example) with Rc set. So let's handle the bit the same way hardware does and ignore it. Signed-off-by: Alexander Graf --- target-ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 84c5cea..fc3251e 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9884,7 +9884,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), -GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), +GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), -- 2.5.0