From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTfZ3-0006v9-TY for qemu-devel@nongnu.org; Sun, 23 Aug 2015 20:24:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZTfZ1-0000gY-AT for qemu-devel@nongnu.org; Sun, 23 Aug 2015 20:24:41 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:43568) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTfZ1-0000gR-6A for qemu-devel@nongnu.org; Sun, 23 Aug 2015 20:24:39 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 1964720956 for ; Sun, 23 Aug 2015 20:24:39 -0400 (EDT) From: "Emilio G. Cota" Date: Sun, 23 Aug 2015 20:23:42 -0400 Message-Id: <1440375847-17603-14-git-send-email-cota@braap.org> In-Reply-To: <1440375847-17603-1-git-send-email-cota@braap.org> References: <1440375847-17603-1-git-send-email-cota@braap.org> Subject: [Qemu-devel] [RFC 13/38] cputlb: add physical address to CPUTLBEntry List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Cc: mark.burton@greensocs.com, a.rigo@virtualopensystems.com, guillaume.delbergue@greensocs.com, pbonzini@redhat.com, alex.bennee@linaro.org, Frederic Konrad Having the physical address in the TLB entry will allow us to portably obtain the physical address of a memory access, which will prove useful when implementing a scalable emulation of atomic instructions. Signed-off-by: Emilio G. Cota --- cputlb.c | 1 + include/exec/cpu-defs.h | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/cputlb.c b/cputlb.c index d1ad8e8..1b3673e 100644 --- a/cputlb.c +++ b/cputlb.c @@ -409,6 +409,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, } else { te->addr_write = -1; } + te->addr_phys = paddr; } /* Add a new TLB entry, but without specifying the memory diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5093be2..ca9c85c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -60,10 +60,10 @@ typedef uint64_t target_ulong; /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 -#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 -#define CPU_TLB_ENTRY_BITS 4 -#else +#if TARGET_LONG_BITS == 32 #define CPU_TLB_ENTRY_BITS 5 +#else +#define CPU_TLB_ENTRY_BITS 6 #endif /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that @@ -110,6 +110,7 @@ typedef struct CPUTLBEntry { target_ulong addr_read; target_ulong addr_write; target_ulong addr_code; + target_ulong addr_phys; /* Addend to virtual address to get host address. IO accesses use the corresponding iotlb value. */ uintptr_t addend; -- 1.9.1