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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: walt@tilera.com, cmetcalf@ezchip.com,
	xili_gchen_5257@hotmail.com, peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions
Date: Mon, 24 Aug 2015 09:17:45 -0700	[thread overview]
Message-ID: <1440433079-14458-20-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1440433079-14458-1-git-send-email-rth@twiddle.net>

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-tilegx/translate.c | 58 +++++++++++++++++++++++++++++++++--------------
 1 file changed, 41 insertions(+), 17 deletions(-)

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 37c6ec5..11dcd45 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -242,7 +242,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
     const char *mnemonic;
     TCGMemOp memop;
 
-    /* Eliminate nops before doing anything else.  */
+    /* Eliminate nops and jumps before doing anything else.  */
     switch (opext) {
     case OE_RR_Y0(NOP):
     case OE_RR_Y1(NOP):
@@ -261,6 +261,31 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         }
         qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
         return TILEGX_EXCP_NONE;
+
+    case OE_RR_X1(JRP):
+    case OE_RR_Y1(JRP):
+        mnemonic = "jrp";
+        goto do_jr;
+    case OE_RR_X1(JR):
+    case OE_RR_Y1(JR):
+        mnemonic = "jr";
+        goto do_jr;
+    case OE_RR_X1(JALRP):
+    case OE_RR_Y1(JALRP):
+        mnemonic = "jalrp";
+        goto do_jalr;
+    case OE_RR_X1(JALR):
+    case OE_RR_Y1(JALR):
+        mnemonic = "jalr";
+    do_jalr:
+        tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
+                        dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+    do_jr:
+        dc->jmp.cond = TCG_COND_ALWAYS;
+        dc->jmp.dest = tcg_temp_new();
+        tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
+        qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
+        return TILEGX_EXCP_NONE;
     }
 
     tdest = dest_gr(dc, dest);
@@ -289,14 +314,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
     case OE_RR_Y1(ILL):
     case OE_RR_X1(INV):
     case OE_RR_X1(IRET):
-    case OE_RR_X1(JALRP):
-    case OE_RR_Y1(JALRP):
-    case OE_RR_X1(JALR):
-    case OE_RR_Y1(JALR):
-    case OE_RR_X1(JRP):
-    case OE_RR_Y1(JRP):
-    case OE_RR_X1(JR):
-    case OE_RR_Y1(JR):
         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     case OE_RR_X1(LD1S):
         memop = MO_SB;
@@ -363,6 +380,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         break;
     case OE_RR_X1(LNK):
     case OE_RR_Y1(LNK):
+        if (srca) {
+            return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+        }
+        tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+        mnemonic = "lnk";
+        break;
     case OE_RR_X1(MF):
     case OE_RR_X1(NAP):
         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
@@ -1086,18 +1109,19 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
     return TILEGX_EXCP_NONE;
 }
 
-static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext,
-                                   int off)
+static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
 {
     target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
-    const char *mnemonic;
+    const char *mnemonic = "j";
 
-    switch (ext) {
-    case JAL_JUMP_OPCODE_X1:
-    case J_JUMP_OPCODE_X1:
-    default:
-        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+    /* The extension field is 1 bit, therefore we only have JAL and J.  */
+    if (ext == JAL_JUMP_OPCODE_X1) {
+        tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
+                        dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+        mnemonic = "jal";
     }
+    dc->jmp.cond = TCG_COND_ALWAYS;
+    dc->jmp.dest = tcg_const_tl(tgt);
 
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("%s " TARGET_FMT_lx " <%s>",
-- 
2.4.3

  parent reply	other threads:[~2015-08-24 16:19 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
2015-08-29 14:29   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-08-24 16:29   ` Peter Maydell
2015-08-24 16:43     ` Richard Henderson
2015-08-26 17:11   ` Chris Metcalf
2015-08-29 14:30   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
2015-08-29 14:37   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
2015-08-29 14:50   ` Peter Maydell
     [not found]     ` <55E24808.5000302@hotmail.com>
2015-08-30  0:01       ` Chen Gang
2015-08-29 21:08   ` Peter Maydell
2015-09-01  1:58     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
2015-08-29 14:51   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
2015-08-29 14:58   ` Peter Maydell
2015-09-01  2:10     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
2015-08-29 15:03   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
2015-08-29 15:26   ` Peter Maydell
2015-09-01  2:26     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
2015-08-29 20:45   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
2015-08-29 20:52   ` Peter Maydell
2015-08-24 16:17 ` Richard Henderson [this message]
2015-08-29 21:00   ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
2015-08-29 21:08   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
2015-08-29 21:12   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
2015-08-29 21:21   ` Peter Maydell
2015-09-01  5:16     ` Richard Henderson
2015-09-01  8:23       ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
2015-08-30 13:31   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Richard Henderson
2015-08-30 13:38   ` Peter Maydell
2015-09-01  5:37     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
2015-08-30 13:40   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
2015-08-30 13:46   ` Peter Maydell
2015-09-01  5:42     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
2015-08-30 13:52   ` Peter Maydell
2015-09-01  5:43     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
2015-08-30 15:11   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
2015-08-30 15:18   ` Peter Maydell
2015-09-01  5:48     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
2015-08-25  4:15   ` Richard Henderson
     [not found]     ` <55DC69B0.1040000@hotmail.com>
2015-08-25 13:11       ` Chen Gang
2015-08-25 13:12         ` Chen Gang
2015-08-25 14:28           ` Richard Henderson
     [not found]             ` <55DCE21F.9000103@hotmail.com>
2015-08-25 21:45               ` Chen Gang
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
2015-08-30 15:20   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
2015-08-30 15:23   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
2015-08-30 15:28   ` Peter Maydell
     [not found] ` <55DB96D7.9000105@hotmail.com>
2015-08-24 22:12   ` [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Chen Gang
     [not found]     ` <55E1B1AF.3040407@hotmail.com>
2015-08-29 13:19       ` Chen Gang
     [not found]         ` <55E2822E.4000805@hotmail.com>
2015-08-30  4:09           ` Chen Gang
2015-09-10 15:29             ` Chen Gang

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