From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37653) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuSl-000341-MZ for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:19:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZTuSi-00030A-Lq for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:19:11 -0400 Received: from mail-qg0-x230.google.com ([2607:f8b0:400d:c04::230]:36752) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuSi-000306-Ig for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:19:08 -0400 Received: by qgeb6 with SMTP id b6so89610221qge.3 for ; Mon, 24 Aug 2015 09:19:08 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 24 Aug 2015 09:17:46 -0700 Message-Id: <1440433079-14458-21-git-send-email-rth@twiddle.net> In-Reply-To: <1440433079-14458-1-git-send-email-rth@twiddle.net> References: <1440433079-14458-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: walt@tilera.com, cmetcalf@ezchip.com, xili_gchen_5257@hotmail.com, peter.maydell@linaro.org Signed-off-by: Richard Henderson --- target-tilegx/translate.c | 51 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 11dcd45..ddeb65f 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1081,30 +1081,55 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext, target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES; const char *mnemonic; - switch (ext) { - case BEQZT_BRANCH_OPCODE_X1: + dc->jmp.dest = tcg_const_tl(tgt); + dc->jmp.val1 = tcg_temp_new(); + tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca)); + + /* Note that the "predict taken" opcodes have bit 0 clear. + Therefore, fold the two cases together by setting bit 0. */ + switch (ext | 1) { case BEQZ_BRANCH_OPCODE_X1: - case BNEZT_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_EQ; + mnemonic = "beqz"; + break; case BNEZ_BRANCH_OPCODE_X1: - case BLBC_BRANCH_OPCODE_X1: - case BGEZT_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_NE; + mnemonic = "bnez"; + break; case BGEZ_BRANCH_OPCODE_X1: - case BGTZT_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_GE; + mnemonic = "bgez"; + break; case BGTZ_BRANCH_OPCODE_X1: - case BLBCT_BRANCH_OPCODE_X1: - case BLBST_BRANCH_OPCODE_X1: - case BLBS_BRANCH_OPCODE_X1: - case BLEZT_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_GT; + mnemonic = "bgtz"; + break; case BLEZ_BRANCH_OPCODE_X1: - case BLTZT_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_LE; + mnemonic = "blez"; + break; case BLTZ_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_LT; + mnemonic = "bltz"; + break; + case BLBC_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_EQ; + tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1); + mnemonic = "blbc"; + break; + case BLBS_BRANCH_OPCODE_X1: + dc->jmp.cond = TCG_COND_NE; + tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1); + mnemonic = "blbs"; + break; default: return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; } if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - qemu_log("%s %s, " TARGET_FMT_lx " <%s>", - mnemonic, reg_names[srca], tgt, lookup_symbol(tgt)); + qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>", + mnemonic, ext & 1 ? "" : "t", + reg_names[srca], tgt, lookup_symbol(tgt)); } return TILEGX_EXCP_NONE; } -- 2.4.3