From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: walt@tilera.com, cmetcalf@ezchip.com,
xili_gchen_5257@hotmail.com, peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions
Date: Mon, 24 Aug 2015 09:17:50 -0700 [thread overview]
Message-ID: <1440433079-14458-25-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1440433079-14458-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 57 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 6be751b..4e6d577 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -474,6 +474,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
TCGv tdest = dest_gr(dc, dest);
TCGv tsrca = load_gr(dc, srca);
TCGv tsrcb = load_gr(dc, srcb);
+ TCGv t0;
const char *mnemonic;
switch (opext) {
@@ -666,7 +667,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
case OE_RRR(ROTL, 6, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_rotl_tl(tdest, tsrca, tdest);
+ mnemonic = "torl";
+ break;
case OE_RRR(SHL1ADDX, 0, X0):
case OE_RRR(SHL1ADDX, 0, X1):
case OE_RRR(SHL1ADDX, 7, Y0):
@@ -720,21 +724,45 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(SHLX, 0, X0):
case OE_RRR(SHLX, 0, X1):
+ tcg_gen_andi_tl(tdest, tsrcb, 31);
+ tcg_gen_shl_tl(tdest, tsrca, tdest);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shlx";
+ break;
case OE_RRR(SHL, 0, X0):
case OE_RRR(SHL, 0, X1):
case OE_RRR(SHL, 6, Y0):
case OE_RRR(SHL, 6, Y1):
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_shl_tl(tdest, tsrca, tdest);
+ mnemonic = "shl";
+ break;
case OE_RRR(SHRS, 0, X0):
case OE_RRR(SHRS, 0, X1):
case OE_RRR(SHRS, 6, Y0):
case OE_RRR(SHRS, 6, Y1):
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_sar_tl(tdest, tsrca, tdest);
+ mnemonic = "shrs";
+ break;
case OE_RRR(SHRUX, 0, X0):
case OE_RRR(SHRUX, 0, X1):
+ t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, tsrcb, 31);
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ tcg_gen_shl_tl(tdest, tdest, t0);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ tcg_temp_free(t0);
+ mnemonic = "shrux";
+ break;
case OE_RRR(SHRU, 0, X0):
case OE_RRR(SHRU, 0, X1):
case OE_RRR(SHRU, 6, Y0):
case OE_RRR(SHRU, 6, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_shr_tl(tdest, tsrca, tdest);
+ mnemonic = "shru";
+ break;
case OE_RRR(SHUFFLEBYTES, 0, X0):
gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
mnemonic = "shufflebytes";
@@ -1068,22 +1096,46 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_SH(ROTLI, X1):
case OE_SH(ROTLI, Y0):
case OE_SH(ROTLI, Y1):
+ tcg_gen_rotli_tl(tdest, tsrca, imm);
+ mnemonic = "rotli";
+ break;
case OE_SH(SHLI, X0):
case OE_SH(SHLI, X1):
case OE_SH(SHLI, Y0):
case OE_SH(SHLI, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, imm);
+ mnemonic = "shli";
+ break;
case OE_SH(SHLXI, X0):
case OE_SH(SHLXI, X1):
+ tcg_gen_shli_tl(tdest, tsrca, imm & 31);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shlxi";
+ break;
case OE_SH(SHRSI, X0):
case OE_SH(SHRSI, X1):
case OE_SH(SHRSI, Y0):
case OE_SH(SHRSI, Y1):
+ tcg_gen_sari_tl(tdest, tsrca, imm);
+ mnemonic = "shrsi";
+ break;
case OE_SH(SHRUI, X0):
case OE_SH(SHRUI, X1):
case OE_SH(SHRUI, Y0):
case OE_SH(SHRUI, Y1):
+ tcg_gen_shri_tl(tdest, tsrca, imm);
+ mnemonic = "shrui";
+ break;
case OE_SH(SHRUXI, X0):
case OE_SH(SHRUXI, X1):
+ if ((imm & 31) == 0) {
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ } else {
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ tcg_gen_shli_tl(tdest, tdest, imm & 31);
+ }
+ mnemonic = "shlxi";
+ break;
case OE_SH(V1SHLI, X0):
case OE_SH(V1SHLI, X1):
case OE_SH(V1SHRSI, X0):
@@ -1096,6 +1148,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_SH(V2SHRSI, X1):
case OE_SH(V2SHRUI, X0):
case OE_SH(V2SHRUI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE(ADDLI_OPCODE_X0, 0, X0):
case OE(ADDLI_OPCODE_X1, 0, X1):
--
2.4.3
next prev parent reply other threads:[~2015-08-24 16:19 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
2015-08-29 14:29 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-08-24 16:29 ` Peter Maydell
2015-08-24 16:43 ` Richard Henderson
2015-08-26 17:11 ` Chris Metcalf
2015-08-29 14:30 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
2015-08-29 14:37 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
2015-08-29 14:50 ` Peter Maydell
[not found] ` <55E24808.5000302@hotmail.com>
2015-08-30 0:01 ` Chen Gang
2015-08-29 21:08 ` Peter Maydell
2015-09-01 1:58 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
2015-08-29 14:51 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
2015-08-29 14:58 ` Peter Maydell
2015-09-01 2:10 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
2015-08-29 15:03 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
2015-08-29 15:26 ` Peter Maydell
2015-09-01 2:26 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
2015-08-29 20:45 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
2015-08-29 20:52 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Richard Henderson
2015-08-29 21:00 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
2015-08-29 21:08 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
2015-08-29 21:12 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
2015-08-29 21:21 ` Peter Maydell
2015-09-01 5:16 ` Richard Henderson
2015-09-01 8:23 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
2015-08-30 13:31 ` Peter Maydell
2015-08-24 16:17 ` Richard Henderson [this message]
2015-08-30 13:38 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Peter Maydell
2015-09-01 5:37 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
2015-08-30 13:40 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
2015-08-30 13:46 ` Peter Maydell
2015-09-01 5:42 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
2015-08-30 13:52 ` Peter Maydell
2015-09-01 5:43 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
2015-08-30 15:11 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
2015-08-30 15:18 ` Peter Maydell
2015-09-01 5:48 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
2015-08-25 4:15 ` Richard Henderson
[not found] ` <55DC69B0.1040000@hotmail.com>
2015-08-25 13:11 ` Chen Gang
2015-08-25 13:12 ` Chen Gang
2015-08-25 14:28 ` Richard Henderson
[not found] ` <55DCE21F.9000103@hotmail.com>
2015-08-25 21:45 ` Chen Gang
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
2015-08-30 15:20 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
2015-08-30 15:23 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
2015-08-30 15:28 ` Peter Maydell
[not found] ` <55DB96D7.9000105@hotmail.com>
2015-08-24 22:12 ` [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Chen Gang
[not found] ` <55E1B1AF.3040407@hotmail.com>
2015-08-29 13:19 ` Chen Gang
[not found] ` <55E2822E.4000805@hotmail.com>
2015-08-30 4:09 ` Chen Gang
2015-09-10 15:29 ` Chen Gang
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