From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37349) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuSM-0002Kg-As for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:18:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZTuSL-0002sD-HR for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:18:46 -0400 Received: from mail-qg0-x229.google.com ([2607:f8b0:400d:c04::229]:34167) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuSL-0002s9-Dm for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:18:45 -0400 Received: by qgeg42 with SMTP id g42so90040199qge.1 for ; Mon, 24 Aug 2015 09:18:45 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 24 Aug 2015 09:17:32 -0700 Message-Id: <1440433079-14458-7-git-send-email-rth@twiddle.net> In-Reply-To: <1440433079-14458-1-git-send-email-rth@twiddle.net> References: <1440433079-14458-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: walt@tilera.com, cmetcalf@ezchip.com, xili_gchen_5257@hotmail.com, peter.maydell@linaro.org Both ADDX_SPECIAL_0_OPCODE_Y1 and ADD_SPECIAL_0_OPCODE_Y1 do not appear to be "special" in any way, except that they don't follow the normal naming convention using _RRR_. Signed-off-by: Richard Henderson --- target-tilegx/opcode_tilegx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h index 33b71a9..3b8bf4f 100644 --- a/target-tilegx/opcode_tilegx.h +++ b/target-tilegx/opcode_tilegx.h @@ -830,11 +830,11 @@ enum ADDX_RRR_0_OPCODE_X0 = 2, ADDX_RRR_0_OPCODE_X1 = 2, ADDX_RRR_0_OPCODE_Y0 = 0, - ADDX_SPECIAL_0_OPCODE_Y1 = 0, + ADDX_RRR_0_OPCODE_Y1 = 0, ADD_RRR_0_OPCODE_X0 = 3, ADD_RRR_0_OPCODE_X1 = 3, ADD_RRR_0_OPCODE_Y0 = 1, - ADD_SPECIAL_0_OPCODE_Y1 = 1, + ADD_RRR_0_OPCODE_Y1 = 1, ANDI_IMM8_OPCODE_X0 = 3, ANDI_IMM8_OPCODE_X1 = 3, ANDI_OPCODE_Y0 = 2, -- 2.4.3