From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
Date: Tue, 25 Aug 2015 16:00:06 +0100 [thread overview]
Message-ID: <1440514816-16562-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org>
Some coprocessor register access functions need to be able
to report "trap to EL3 with an 'uncategorized' syndrome";
add the necessary CPAccessResult enum and handling for it.
I don't currently know of any registers that need to trap
to EL2 with the 'uncategorized' syndrome, but adding the
_EL2 enum as well is trivial and fills in what would
otherwise be an odd gap in the handling.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1437751263-21913-4-git-send-email-peter.maydell@linaro.org
---
target-arm/cpu.h | 3 +++
target-arm/op_helper.c | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2e680da..31825d3 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1284,6 +1284,9 @@ typedef enum CPAccessResult {
/* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
CP_ACCESS_TRAP_EL2 = 3,
CP_ACCESS_TRAP_EL3 = 4,
+ /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
+ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
+ CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
} CPAccessResult;
/* Access functions for coprocessor registers. These cannot fail and
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 663c05d..1425a1d 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -444,6 +444,14 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
target_el = exception_target_el(env);
syndrome = syn_uncategorized();
break;
+ case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
+ target_el = 2;
+ syndrome = syn_uncategorized();
+ break;
+ case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
+ target_el = 3;
+ syndrome = syn_uncategorized();
+ break;
default:
g_assert_not_reached();
}
--
1.9.1
next prev parent reply other threads:[~2015-08-25 15:00 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-25 14:59 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2015-08-25 14:59 ` [Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks Peter Maydell
2015-08-25 14:59 ` [Qemu-devel] [PULL 02/20] MAINTAINERS: Update Xilinx Maintainership Peter Maydell
2015-08-25 14:59 ` [Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops Peter Maydell
2015-08-25 15:00 ` Peter Maydell [this message]
2015-08-25 15:00 ` [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 15/20] cputlb: Add functions for flushing TLB for a single MMU index Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs Peter Maydell
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