From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35415) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFi9-0001ja-D1 for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUFi8-0001XK-Bu for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:29 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34989) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFi8-0001NR-5G for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:28 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZUFhx-0004KT-CV for qemu-devel@nongnu.org; Tue, 25 Aug 2015 16:00:17 +0100 From: Peter Maydell Date: Tue, 25 Aug 2015 16:00:07 +0100 Message-Id: <1440514816-16562-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> References: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Apply the correct conditions in the ats_access() function for the ATS12NSO* address translation operations: * succeed at EL2 or EL3 * normal UNDEF trap from NS EL1 * trap to EL3 from S EL1 (only possible if EL3 is AArch64) (This change means they're now available in our EL3-supporting CPUs when they would previously always UNDEF.) Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 8603660..4b2fc090 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1719,12 +1719,17 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) { if (ri->opc2 & 4) { - /* Other states are only available with TrustZone; in - * a non-TZ implementation these registers don't exist - * at all, which is an Uncategorized trap. This underdecoding - * is safe because the reginfo is NO_RAW. + /* The ATS12NSO* operations must trap to EL3 if executed in + * Secure EL1 (which can only happen if EL3 is AArch64). + * They are simply UNDEF if executed from NS EL1. + * They function normally from EL2 or EL3. */ - return CP_ACCESS_TRAP_UNCATEGORIZED; + if (arm_current_el(env) == 1) { + if (arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; + } } return CP_ACCESS_OK; } @@ -1899,6 +1904,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { offsetoflow32(CPUARMState, cp15.par_ns) }, .writefn = par_write }, #ifndef CONFIG_USER_ONLY + /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, .writefn = ats_write, .type = ARM_CP_NO_RAW }, -- 1.9.1