From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFi9-0001ik-0i for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUFi8-0001X4-2B for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:28 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34989) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFi7-0001NR-RV for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:27 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZUFhx-0004KY-EF for qemu-devel@nongnu.org; Tue, 25 Aug 2015 16:00:17 +0100 From: Peter Maydell Date: Tue, 25 Aug 2015 16:00:08 +0100 Message-Id: <1440514816-16562-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> References: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Implement the AArch32 ATS1H* operations which perform Hyp mode stage 1 translations. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1437751263-21913-6-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4b2fc090..6c55cc4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1849,6 +1849,17 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) A32_BANKED_CURRENT_REG_SET(env, par, par64); } +static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int access_type = ri->opc2 & 1; + uint64_t par64; + + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri) { if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { @@ -3066,6 +3077,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, .accessfn = at_s1e2_access, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 + * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose + * to behave as if SCR.NS was 1. + */ + { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, + .access = PL2_W, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, + { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, + .access = PL2_W, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the -- 1.9.1