From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file
Date: Tue, 25 Aug 2015 15:59:59 +0100 [thread overview]
Message-ID: <1440514816-16562-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org>
From: Alistair Francis <alistair.francis@xilinx.com>
Add the Xilinx ZynqMP SoC and EP108 machine to the maintainers
file.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fed078103a0b02cfb3adadbe8e80e4420d554505.1436486024.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d0268f9..08f356a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -357,6 +357,14 @@ F: hw/misc/zynq_slcr.c
F: hw/*/cadence_*
F: hw/ssi/xilinx_spips.c
+Xilinx ZynqMP
+M: Alistair Francis <alistair.francis@xilinx.com>
+M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
+S: Maintained
+F: hw/arm/xlnx-zynqmp.c
+F: hw/arm/xlnx-ep108.c
+F: include/hw/arm/xlnx-zynqmp.h
+
ARM ACPI Subsystem
M: Shannon Zhao <zhaoshenglong@huawei.com>
M: Shannon Zhao <shannon.zhao@linaro.org>
--
1.9.1
next prev parent reply other threads:[~2015-08-25 15:00 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-25 14:59 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2015-08-25 14:59 ` [Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks Peter Maydell
2015-08-25 14:59 ` [Qemu-devel] [PULL 02/20] MAINTAINERS: Update Xilinx Maintainership Peter Maydell
2015-08-25 14:59 ` Peter Maydell [this message]
2015-08-25 15:00 ` [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 15/20] cputlb: Add functions for flushing TLB for a single MMU index Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations Peter Maydell
2015-08-25 15:00 ` [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs Peter Maydell
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