From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFiB-0001m2-DF for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUFiA-0001ZW-5h for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:31 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34989) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFi9-0001NR-R3 for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:30 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZUFhx-0004K4-2S for qemu-devel@nongnu.org; Tue, 25 Aug 2015 16:00:17 +0100 From: Peter Maydell Date: Tue, 25 Aug 2015 16:00:02 +0100 Message-Id: <1440514816-16562-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> References: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The AFSR registers are implementation dependent auxiliary fault status registers. We already implemented a RAZ/WI AFSR0_EL1 and AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1438281398-18746-4-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 54f99ae..f6119be 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2848,6 +2848,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -2972,6 +2980,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .writefn = vmsa_tcr_el1_write, @@ -3118,6 +3134,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, REGINFO_SENTINEL }; -- 1.9.1