[Qemu-devel] [PULL 00/18] target-arm queue

[Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

Here's the ARM queue. I know I have a pile of backed-up code
review to do, but I wanted to get these patches out rather
than accumulating a fifty-patch queue...

This is v2: only change is to drop the two smbios patches.

thanks
-- PMM


The following changes since commit 34a4450434f1a5daee06fca223afcbb9c8f1ee24:

  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into staging (2015-08-25 13:34:57 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150825-1

for you to fetch changes up to cea66e91212164e02ad1d245c2371f7e8eb59e7f:

  target-arm: Implement AArch64 TLBI operations on IPAs (2015-08-25 16:18:33 +0100)

----------------------------------------------------------------
target-arm queue:
 * add missing EL2/EL3 TLBI operations
 * add missing EL2/EL3 ATS operations
 * add missing EL2/EL3 registers
 * update Xilinx MAINTAINERS info
 * Xilinx: connect the four OCM banks

----------------------------------------------------------------
Alistair Francis (3):
      xlnx-zynqmp: Connect the four OCM banks
      MAINTAINERS: Update Xilinx Maintainership
      MAINTAINERS: Add ZynqMP to MAINTAINERS file

Peter Maydell (15):
      target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
      target-arm: Implement missing AMAIR registers
      target-arm: Implement missing AFSR registers
      target-arm: Implement missing ACTLR registers
      target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
      target-arm: Wire up AArch64 EL2 and EL3 address translation ops
      target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
      target-arm: Enable the AArch32 ATS12NSO ops
      target-arm: Implement AArch32 ATS1H* operations
      cputlb: Add functions for flushing TLB for a single MMU index
      target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
      target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
      target-arm: Implement missing EL2 TLBI operations
      target-arm: Implement missing EL3 TLB invalidate operations
      target-arm: Implement AArch64 TLBI operations on IPAs

 MAINTAINERS                  |  27 ++-
 cputlb.c                     |  97 +++++++++
 hw/arm/xlnx-zynqmp.c         |  15 ++
 include/exec/exec-all.h      |  47 +++++
 include/hw/arm/xlnx-zynqmp.h |   6 +
 target-arm/cpu.h             |   3 +
 target-arm/helper.c          | 489 ++++++++++++++++++++++++++++++++++++++-----
 target-arm/op_helper.c       |   8 +
 8 files changed, 629 insertions(+), 63 deletions(-)

Re: [Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

On 25 August 2015 at 16:23, Peter Maydell <peter.maydell@linaro.org> wrote:
> Here's the ARM queue. I know I have a pile of backed-up code
> review to do, but I wanted to get these patches out rather
> than accumulating a fifty-patch queue...
>
> This is v2: only change is to drop the two smbios patches.

v2 applied to master.

-- PMM

[Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

Collection of patches before softfreeze:
 * some minor bug fixes
 * ASPEED SCU
 * the m25p80 patchset

The following changes since commit aa8151b7df6b1c521b46583badfec504715018c5:

  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160627' into staging (2016-06-27 12:54:54 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160627

for you to fetch changes up to 3830c7a460b8252dc975f8115fdaed8c562d2d75:

  m25p80: Fix WINBOND fast read command handling (2016-06-27 15:37:34 +0100)

----------------------------------------------------------------
target-arm queue:
 * arm_gicv3: add missing 'break' statements
 * cadence_uart: protect against transmit errors
 * cadence_gem: avoid infinite loops with misconfigured buffer
 * cadence_gem: set the 'last' bit when 'wrap' is set
 * reenable tmp105 test case
 * palmetto-bmc: add ASPEED system control unit model
 * m25p80: add new 512Mbit and 1Gbit devices

----------------------------------------------------------------
Alistair Francis (3):
      cadence_uart: Protect against transmit errors
      cadence_gem: Avoid infinite loops with a misconfigured buffer
      cadence_gem: Set the last bit when wrap is set

Andrew Jeffery (3):
      hw/misc: Add a model for the ASPEED System Control Unit
      ast2400: Integrate the SCU model and set silicon revision
      palmetto-bmc: Configure the SCU's hardware strapping register

Marcin Krzeminski (10):
      m25p80: Replace JEDEC ID masking with function.
      m25p80: Make a table for JEDEC ID.
      m25p80: Allow more than four banks.
      m25p80: Introduce COLLECTING_VAR_LEN_DATA state.
      m25p80: Add additional flash commands:
      m25p80: Introduce quad and equad modes.
      m25p80: Introduce configuration registers.
      m25p80: Fast read commands family changes.
      m25p80: New flash devices.
      m25p80: Fix WINBOND fast read command handling

Shannon Zhao (1):
      hw/intc/arm_gicv3: Add missing break

Thomas Huth (1):
      arm: Re-enable tmp105 test

 hw/arm/ast2400.c             |  21 +++
 hw/arm/palmetto-bmc.c        |   2 +
 hw/block/m25p80.c            | 398 +++++++++++++++++++++++++++++++++++--------
 hw/char/cadence_uart.c       |   7 +-
 hw/intc/arm_gicv3_cpuif.c    |   2 +
 hw/misc/Makefile.objs        |   1 +
 hw/misc/aspeed_scu.c         | 283 ++++++++++++++++++++++++++++++
 hw/misc/trace-events         |   3 +
 hw/net/cadence_gem.c         |  13 ++
 include/hw/arm/ast2400.h     |   2 +
 include/hw/misc/aspeed_scu.h |  34 ++++
 tests/Makefile.include       |   2 +-
 12 files changed, 698 insertions(+), 70 deletions(-)
 create mode 100644 hw/misc/aspeed_scu.c
 create mode 100644 include/hw/misc/aspeed_scu.h

Re: [Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

On 27 June 2016 at 15:44, Peter Maydell <peter.maydell@linaro.org> wrote:
> Collection of patches before softfreeze:
>  * some minor bug fixes
>  * ASPEED SCU
>  * the m25p80 patchset
>
> The following changes since commit aa8151b7df6b1c521b46583badfec504715018c5:
>
>   Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160627' into staging (2016-06-27 12:54:54 +0100)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160627
>
> for you to fetch changes up to 3830c7a460b8252dc975f8115fdaed8c562d2d75:
>
>   m25p80: Fix WINBOND fast read command handling (2016-06-27 15:37:34 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * arm_gicv3: add missing 'break' statements
>  * cadence_uart: protect against transmit errors
>  * cadence_gem: avoid infinite loops with misconfigured buffer
>  * cadence_gem: set the 'last' bit when 'wrap' is set
>  * reenable tmp105 test case
>  * palmetto-bmc: add ASPEED system control unit model
>  * m25p80: add new 512Mbit and 1Gbit devices

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

ARM queue for 2.10 soft freeze...

thanks
-- PMM

The following changes since commit 6632f6ff96f0537fc34cdc00c760656fc62e23c5:

  Merge remote-tracking branch 'remotes/famz/tags/block-and-testing-pull-request' into staging (2017-07-17 11:46:36 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170717

for you to fetch changes up to e5a6a6e64e82a132cebef023d867085b0a2993d7:

  MAINTAINERS: Add entries for MPS2 board (2017-07-17 13:36:09 +0100)

----------------------------------------------------------------
target-arm queue:
 * new model of the ARM MPS2/MPS2+ FPGA based development board
 * clean up DISAS_* exit conditions and fix various regressions
   since commits e75449a346 8a6b28c7b5 (in particular including
   ones which broke OP-TEE guests)
 * make Cortex-M3 and M4 correctly default to 8 PMSA regions

----------------------------------------------------------------
Alex Bennée (6):
      include/exec/exec-all: document common exit conditions
      target/arm/translate: make DISAS_UPDATE match declared semantics
      target/arm/translate.h: expand comment on DISAS_EXIT
      target/arm/translate: ensure gen_goto_tb sets exit flags
      target/arm: use gen_goto_tb for ISB handling
      target/arm: use DISAS_EXIT for eret handling

Peter Maydell (12):
      qdev-properties.h: Explicitly set the default value for arraylen properties
      qdev: support properties which don't set a default value
      target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions
      hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models
      hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART
      hw/arm/mps2: Add UARTs
      hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device
      hw/arm/mps2: Add timers
      hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller
      hw/arm/mps2: Add SCC
      hw/arm/mps2: Add ethernet
      MAINTAINERS: Add entries for MPS2 board

 hw/arm/Makefile.objs               |   1 +
 hw/char/Makefile.objs              |   1 +
 hw/misc/Makefile.objs              |   1 +
 hw/timer/Makefile.objs             |   1 +
 include/exec/exec-all.h            |  29 ++-
 include/hw/char/cmsdk-apb-uart.h   |  78 +++++++
 include/hw/misc/mps2-scc.h         |  43 ++++
 include/hw/qdev-core.h             |  10 +
 include/hw/qdev-properties.h       |  21 ++
 include/hw/timer/cmsdk-apb-timer.h |  59 ++++++
 target/arm/translate.h             |   5 +-
 hw/arm/mps2.c                      | 385 +++++++++++++++++++++++++++++++++++
 hw/char/cmsdk-apb-uart.c           | 403 +++++++++++++++++++++++++++++++++++++
 hw/core/qdev.c                     |   2 +-
 hw/misc/mps2-scc.c                 | 310 ++++++++++++++++++++++++++++
 hw/timer/cmsdk-apb-timer.c         | 253 +++++++++++++++++++++++
 target/arm/cpu.c                   |  12 +-
 target/arm/translate-a64.c         |  19 +-
 target/arm/translate.c             |  22 +-
 MAINTAINERS                        |  14 +-
 default-configs/arm-softmmu.mak    |   6 +
 hw/char/trace-events               |   9 +
 hw/misc/trace-events               |   8 +
 hw/timer/trace-events              |   5 +
 24 files changed, 1673 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/char/cmsdk-apb-uart.h
 create mode 100644 include/hw/misc/mps2-scc.h
 create mode 100644 include/hw/timer/cmsdk-apb-timer.h
 create mode 100644 hw/arm/mps2.c
 create mode 100644 hw/char/cmsdk-apb-uart.c
 create mode 100644 hw/misc/mps2-scc.c
 create mode 100644 hw/timer/cmsdk-apb-timer.c

Re: [Qemu-devel] [PULL 00/18] target-arm queue

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PULL 00/18] target-arm queue
Message-id: 1500295494-8991-1-git-send-email-peter.maydell@linaro.org
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20170717110936.23314-1-dgilbert@redhat.com -> patchew/20170717110936.23314-1-dgilbert@redhat.com
Switched to a new branch 'test'
f4eface MAINTAINERS: Add entries for MPS2 board
f1fecfb hw/arm/mps2: Add ethernet
5cc8e71 hw/arm/mps2: Add SCC
5404d5a hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller
3b85601 hw/arm/mps2: Add timers
8784008 hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device
d7ae3d4 hw/arm/mps2: Add UARTs
41c0f2d hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART
c7eb8eb hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models
bdd7af5 target/arm: use DISAS_EXIT for eret handling
ec55bc9 target/arm: use gen_goto_tb for ISB handling
dabdd10 target/arm/translate: ensure gen_goto_tb sets exit flags
759a7d2 target/arm/translate.h: expand comment on DISAS_EXIT
538a900 target/arm/translate: make DISAS_UPDATE match declared semantics
c4d68d9 include/exec/exec-all: document common exit conditions
2d96cb8 target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions
0793ffd qdev: support properties which don't set a default value
90ea21c qdev-properties.h: Explicitly set the default value for arraylen properties

=== OUTPUT BEGIN ===
Checking PATCH 1/18: qdev-properties.h: Explicitly set the default value for arraylen properties...
Checking PATCH 2/18: qdev: support properties which don't set a default value...
Checking PATCH 3/18: target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions...
Checking PATCH 4/18: include/exec/exec-all: document common exit conditions...
Checking PATCH 5/18: target/arm/translate: make DISAS_UPDATE match declared semantics...
Checking PATCH 6/18: target/arm/translate.h: expand comment on DISAS_EXIT...
Checking PATCH 7/18: target/arm/translate: ensure gen_goto_tb sets exit flags...
Checking PATCH 8/18: target/arm: use gen_goto_tb for ISB handling...
Checking PATCH 9/18: target/arm: use DISAS_EXIT for eret handling...
Checking PATCH 10/18: hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models...
ERROR: line over 90 characters
#77: FILE: hw/arm/mps2.c:22:
+ *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system

total: 1 errors, 0 warnings, 281 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 11/18: hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART...
ERROR: line over 90 characters
#62: FILE: hw/char/cmsdk-apb-uart.c:15:
+ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit

total: 1 errors, 0 warnings, 508 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 12/18: hw/arm/mps2: Add UARTs...
Checking PATCH 13/18: hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device...
ERROR: line over 90 characters
#57: FILE: hw/timer/cmsdk-apb-timer.c:15:
+ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit

total: 1 errors, 0 warnings, 331 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 14/18: hw/arm/mps2: Add timers...
Checking PATCH 15/18: hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller...
ERROR: line over 90 characters
#70: FILE: hw/misc/mps2-scc.c:16:
+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html

ERROR: spaces required around that '*' (ctx:WxV)
#105: FILE: hw/misc/mps2-scc.c:51:
+static bool scc_cfg_write(MPS2SCC *s, unsigned function,
                                   ^

total: 2 errors, 0 warnings, 379 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 16/18: hw/arm/mps2: Add SCC...
Checking PATCH 17/18: hw/arm/mps2: Add ethernet...
Checking PATCH 18/18: MAINTAINERS: Add entries for MPS2 board...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org

Re: [Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

On 17 July 2017 at 13:44, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue for 2.10 soft freeze...
>
> thanks
> -- PMM
>
> The following changes since commit 6632f6ff96f0537fc34cdc00c760656fc62e23c5:
>
>   Merge remote-tracking branch 'remotes/famz/tags/block-and-testing-pull-request' into staging (2017-07-17 11:46:36 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170717
>
> for you to fetch changes up to e5a6a6e64e82a132cebef023d867085b0a2993d7:
>
>   MAINTAINERS: Add entries for MPS2 board (2017-07-17 13:36:09 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * new model of the ARM MPS2/MPS2+ FPGA based development board
>  * clean up DISAS_* exit conditions and fix various regressions
>    since commits e75449a346 8a6b28c7b5 (in particular including
>    ones which broke OP-TEE guests)
>  * make Cortex-M3 and M4 correctly default to 8 PMSA regions
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

ARM queue: nothing particularly exciting, but 18 patches
is enough to send out.

thanks
-- PMM

The following changes since commit 3dabde1128b671f36ac6cb36b97b273139964420:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170914' into staging (2017-09-14 16:33:02 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170914

for you to fetch changes up to ce3bc112cdb1d462e2d52eaa17a7314e7f3af504:

  mps2-an511: Fix wiring of UART overflow interrupt lines (2017-09-14 18:43:19 +0100)

----------------------------------------------------------------
target-arm queue:
 * v7M: various code cleanups
 * v7M: set correct BFSR bits on bus fault
 * v7M: clear exclusive monitor on reset and exception entry/exit
 * v7M: don't apply priority mask to negative priorities
 * zcu102: support 'secure' and 'virtualization' machine properties
 * aarch64: fix ERET single stepping
 * gpex: implement PCI INTx routing
 * mps2-an511: fix UART overflow interrupt line wiring

----------------------------------------------------------------
Alistair Francis (5):
      xlnx-ep108: Rename to ZCU102
      xlnx-zcu102: Manually create the machines
      xlnx-zcu102: Add a machine level secure property
      xlnx-zcu102: Add a machine level virtualization property
      xlnx-zcu102: Mark the EP108 machine as deprecated

Jaroslaw Pelczar (1):
      AArch64: Fix single stepping of ERET instruction

Peter Maydell (8):
      target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2
      target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
      target/arm: Get PRECISERR and IBUSERR the right way round
      nvic: Don't apply group priority mask to negative priorities
      target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()
      target/arm: Add and use defines for EXCRET constants
      target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()
      mps2-an511: Fix wiring of UART overflow interrupt lines

Pranavkumar Sawargaonkar (3):
      hw/pci-host/gpex: Set INTx index/gsi mapping
      hw/arm/virt: Set INTx/gsi mapping
      hw/pci-host/gpex: Implement PCI INTx routing

Richard Henderson (1):
      target/arm: Avoid an extra temporary for store_exclusive

 hw/arm/Makefile.objs         |   2 +-
 include/hw/arm/xlnx-zynqmp.h |   2 +
 include/hw/pci-host/gpex.h   |   3 +
 target/arm/cpu.h             |  35 +++---
 target/arm/internals.h       |  20 ++++
 hw/arm/mps2.c                |   4 +-
 hw/arm/virt.c                |   1 +
 hw/arm/xlnx-ep108.c          | 139 -----------------------
 hw/arm/xlnx-zcu102.c         | 259 +++++++++++++++++++++++++++++++++++++++++++
 hw/arm/xlnx-zynqmp.c         |   3 +-
 hw/intc/armv7m_nvic.c        |  11 +-
 hw/pci-host/gpex.c           |  22 ++++
 target/arm/cpu.c             |   6 +
 target/arm/helper.c          |  43 ++++---
 target/arm/op_helper.c       |   2 +-
 target/arm/translate-a64.c   |  27 ++---
 16 files changed, 382 insertions(+), 197 deletions(-)
 delete mode 100644 hw/arm/xlnx-ep108.c
 create mode 100644 hw/arm/xlnx-zcu102.c

Re: [Qemu-devel] [PULL 00/18] target-arm queue

[Peter Maydell]

On 14 September 2017 at 18:52, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue: nothing particularly exciting, but 18 patches
> is enough to send out.
>
> thanks
> -- PMM
>
> The following changes since commit 3dabde1128b671f36ac6cb36b97b273139964420:
>
>   Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170914' into staging (2017-09-14 16:33:02 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170914
>
> for you to fetch changes up to ce3bc112cdb1d462e2d52eaa17a7314e7f3af504:
>
>   mps2-an511: Fix wiring of UART overflow interrupt lines (2017-09-14 18:43:19 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * v7M: various code cleanups
>  * v7M: set correct BFSR bits on bus fault
>  * v7M: clear exclusive monitor on reset and exception entry/exit
>  * v7M: don't apply priority mask to negative priorities
>  * zcu102: support 'secure' and 'virtualization' machine properties
>  * aarch64: fix ERET single stepping
>  * gpex: implement PCI INTx routing
>  * mps2-an511: fix UART overflow interrupt line wiring
>

Applied, thanks.

-- PMM