From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUsva-0005e8-2N for qemu-devel@nongnu.org; Thu, 27 Aug 2015 04:52:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUsvW-0001cS-P3 for qemu-devel@nongnu.org; Thu, 27 Aug 2015 04:52:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33741) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUsvW-0001c1-Jd for qemu-devel@nongnu.org; Thu, 27 Aug 2015 04:52:54 -0400 Date: Thu, 27 Aug 2015 11:52:51 +0300 From: "Michael S. Tsirkin" Message-ID: <1440665434-2893-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH 1/2] pci: add bar sizing List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, qemu-devel@nongnu.org Will be used for pci-testdev. Signed-off-by: Michael S. Tsirkin --- lib/x86/pci.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/lib/x86/pci.c b/lib/x86/pci.c index 231668a..5116dac 100644 --- a/lib/x86/pci.c +++ b/lib/x86/pci.c @@ -19,6 +19,13 @@ static uint32_t pci_config_read(pcidevaddr_t dev, uint8_t reg) return inl(0xCFC); } +static uint32_t pci_config_write(pcidevaddr_t dev, uint8_t reg, uint32_t val) +{ + uint32_t index = reg | (dev << 8) | (0x1 << 31); + outl(0xCF8, index); + outl(0xCFC, val); +} + /* Scan bus look for a specific device. Only bus 0 scanned for now. */ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id) { @@ -42,6 +49,22 @@ unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num) } } +unsigned long pci_bar_size(pcidevaddr_t dev, int bar_num) +{ + uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4); + uint32_t mask; + + pci_config_write(dev, PCI_BASE_ADDRESS_0 + bar_num * 4, 0xffffffff); + mask = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4); + pci_config_write(dev, PCI_BASE_ADDRESS_0 + bar_num * 4, bar); + + if (bar & PCI_BASE_ADDRESS_SPACE_IO) { + return ~(mask & PCI_BASE_ADDRESS_IO_MASK) + 1; + } else { + return ~(mask & PCI_BASE_ADDRESS_MEM_MASK) + 1; + } +} + bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num) { uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4); -- MST