From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZX0yS-0003Tx-Iq for qemu-devel@nongnu.org; Wed, 02 Sep 2015 01:52:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZX0yR-0004JM-Ok for qemu-devel@nongnu.org; Wed, 02 Sep 2015 01:52:44 -0400 Received: from mail-qg0-x234.google.com ([2607:f8b0:400d:c04::234]:36228) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZX0yR-0004J5-Kz for qemu-devel@nongnu.org; Wed, 02 Sep 2015 01:52:43 -0400 Received: by qgx61 with SMTP id 61so11882597qgx.3 for ; Tue, 01 Sep 2015 22:52:43 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 1 Sep 2015 22:51:47 -0700 Message-Id: <1441173123-25540-5-git-send-email-rth@twiddle.net> In-Reply-To: <1441173123-25540-1-git-send-email-rth@twiddle.net> References: <1441173123-25540-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 04/20] target-arm: Add condexec state to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: dl.soluz@gmx.net, atar4qemu@gmail.com, aurelien@aurel32.net Signed-off-by: Richard Henderson --- target-arm/cpu.h | 1 + target-arm/translate-a64.c | 2 +- target-arm/translate.c | 3 ++- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 31825d3..8d5ae3e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -96,6 +96,7 @@ struct arm_boot_info; #define NB_MMU_MODES 7 +#define TARGET_INSN_START_EXTRA_WORDS 1 /* We currently assume float and double are IEEE single and double precision respectively. diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 48c34d1..4fb4a9f 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11021,7 +11021,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->pc, 0); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); diff --git a/target-arm/translate.c b/target-arm/translate.c index 8fc7edd..c9de455 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11312,7 +11312,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1)); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); -- 2.4.3