From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42153) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZX0yU-0003WL-V3 for qemu-devel@nongnu.org; Wed, 02 Sep 2015 01:52:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZX0yU-0004Jy-7U for qemu-devel@nongnu.org; Wed, 02 Sep 2015 01:52:46 -0400 Received: from mail-qg0-x22d.google.com ([2607:f8b0:400d:c04::22d]:35509) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZX0yU-0004Jt-3a for qemu-devel@nongnu.org; Wed, 02 Sep 2015 01:52:46 -0400 Received: by qgt47 with SMTP id 47so11867772qgt.2 for ; Tue, 01 Sep 2015 22:52:45 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 1 Sep 2015 22:51:49 -0700 Message-Id: <1441173123-25540-7-git-send-email-rth@twiddle.net> In-Reply-To: <1441173123-25540-1-git-send-email-rth@twiddle.net> References: <1441173123-25540-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 06/20] target-mips: Add delayed branch state to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: dl.soluz@gmx.net, atar4qemu@gmail.com, aurelien@aurel32.net Signed-off-by: Richard Henderson --- target-mips/cpu.h | 1 + target-mips/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c91883d..0a53568 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -132,6 +132,7 @@ struct CPUMIPSFPUContext { }; #define NB_MMU_MODES 3 +#define TARGET_INSN_START_EXTRA_WORDS 2 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { diff --git a/target-mips/translate.c b/target-mips/translate.c index 9226420..320adef 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20175,6 +20175,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.CP0_Config1 = env->CP0_Config1; ctx.tb = tb; ctx.bstate = BS_NONE; + ctx.btarget = 0; ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3; @@ -20230,7 +20231,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(ctx.pc); + tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); -- 2.4.3