[Qemu-devel] [PATCH v2 00/11] target-arm improvements for aarch64

[Richard Henderson <rth@twiddle.net>]

Version 1 was posted back in February.  At the time, Peter was
less than thrilled about extending the aarch64 NZCV tcg temps
to 64 bits.  This revision drops that change, and so should be
less controversial.

The tree has also been updated to mainline, which means that
we now have tcg_gen_extrh_i64_i32 available to us, which allows
one more bit of tidying up.


r~


Richard Henderson (11):
  target-arm: Share all common TCG temporaries
  target-arm: Introduce DisasCompare
  target-arm: Handle always condition codes within arm_test_cc
  target-arm: Use setcond and movcond for csel
  target-arm: Implement ccmp branchless
  target-arm: Implement fcsel with movcond
  target-arm: Recognize SXTB, SXTH, SXTW, ASR
  target-arm: Recognize UXTB, UXTH, LSR, LSL
  target-arm: Eliminate unnecessary zero-extend in disas_bitfield
  target-arm: Recognize ROR
  target-arm: Use tcg_gen_extrh_i64_i32

 target-arm/translate-a64.c | 336 ++++++++++++++++++++++++++-------------------
 target-arm/translate.c     | 129 ++++++++++-------
 target-arm/translate.h     |  17 +++
 3 files changed, 286 insertions(+), 196 deletions(-)

-- 
2.4.3