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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v2 03/11] target-arm: Handle always condition codes within arm_test_cc
Date: Wed,  2 Sep 2015 10:57:32 -0700	[thread overview]
Message-ID: <1441216660-8717-4-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1441216660-8717-1-git-send-email-rth@twiddle.net>

Handling this with TCG_COND_ALWAYS will allow these unlikely
cases to be handled without special cases in the rest of the
translator.  The TCG optimizer ought to be able to reduce
these ALWAYS conditions completely.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 1f43777..e2bccef 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -799,6 +799,14 @@ void arm_test_cc(DisasCompare *cmp, int cc)
         tcg_gen_andc_i32(value, cpu_ZF, value);
         break;
 
+    case 14: /* always */
+    case 15: /* always */
+        /* Use the ALWAYS condition, which will fold early.
+           It doesn't matter what we use for the value.  */
+        cond = TCG_COND_ALWAYS;
+        value = cpu_ZF;
+        goto no_invert;
+
     default:
         fprintf(stderr, "Bad condition code 0x%x\n", cc);
         abort();
@@ -808,6 +816,7 @@ void arm_test_cc(DisasCompare *cmp, int cc)
         cond = tcg_invert_cond(cond);
     }
 
+ no_invert:
     cmp->cond = cond;
     cmp->value = value;
     cmp->value_global = global;
-- 
2.4.3

  parent reply	other threads:[~2015-09-02 17:57 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-02 17:57 [Qemu-devel] [PATCH v2 00/11] target-arm improvements for aarch64 Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 01/11] target-arm: Share all common TCG temporaries Richard Henderson
2015-09-07 16:57   ` Peter Maydell
2015-09-08  5:13     ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 02/11] target-arm: Introduce DisasCompare Richard Henderson
2015-09-07 17:09   ` Peter Maydell
2015-09-08  5:09     ` Richard Henderson
2015-09-08  8:13       ` Peter Maydell
2015-09-02 17:57 ` Richard Henderson [this message]
2015-09-07 17:11   ` [Qemu-devel] [PATCH v2 03/11] target-arm: Handle always condition codes within arm_test_cc Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-09-07 17:17   ` Peter Maydell
2015-09-08  5:12     ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless Richard Henderson
2015-09-07 17:31   ` Peter Maydell
2015-09-08  5:18     ` Richard Henderson
2015-09-08  8:19       ` Peter Maydell
2015-09-08 15:20         ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-09-07 17:42   ` Peter Maydell
2015-09-08 15:21     ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Richard Henderson
2015-09-07 17:47   ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-09-07 18:00   ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-09-07 18:02   ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 10/11] target-arm: Recognize ROR Richard Henderson
2015-09-07 18:06   ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32 Richard Henderson
2015-09-07 18:11   ` Peter Maydell

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