From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR
Date: Wed, 2 Sep 2015 10:57:36 -0700 [thread overview]
Message-ID: <1441216660-8717-8-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1441216660-8717-1-git-send-email-rth@twiddle.net>
... as aliases of SBFM, and special-case them.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index a6e5ccd..74dd0f8 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2999,7 +2999,28 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
tcg_rd = cpu_reg(s, rd);
tcg_tmp = read_cpu_reg(s, rn, sf);
- /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
+ /* Recognize the common aliases. */
+ if (opc == 0) { /* SBFM */
+ if (ri == 0) {
+ if (si == 7) { /* SXTB */
+ tcg_gen_ext8s_i64(tcg_rd, tcg_tmp);
+ goto done;
+ } else if (si == 15) { /* SXTH */
+ tcg_gen_ext16s_i64(tcg_rd, tcg_tmp);
+ goto done;
+ } else if (si == 31) { /* SXTW */
+ tcg_gen_ext32s_i64(tcg_rd, tcg_tmp);
+ goto done;
+ }
+ }
+ if (si == 63 || (si == 31 && ri <= si)) { /* ASR */
+ if (si == 31) {
+ tcg_gen_ext32s_i64(tcg_tmp, tcg_tmp);
+ }
+ tcg_gen_sari_i64(tcg_rd, tcg_tmp, ri);
+ goto done;
+ }
+ }
if (opc != 1) { /* SBFM or UBFM */
tcg_gen_movi_i64(tcg_rd, 0);
@@ -3024,6 +3045,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
}
+ done:
if (!sf) { /* zero extend final result */
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
--
2.4.3
next prev parent reply other threads:[~2015-09-02 17:57 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 17:57 [Qemu-devel] [PATCH v2 00/11] target-arm improvements for aarch64 Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 01/11] target-arm: Share all common TCG temporaries Richard Henderson
2015-09-07 16:57 ` Peter Maydell
2015-09-08 5:13 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 02/11] target-arm: Introduce DisasCompare Richard Henderson
2015-09-07 17:09 ` Peter Maydell
2015-09-08 5:09 ` Richard Henderson
2015-09-08 8:13 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 03/11] target-arm: Handle always condition codes within arm_test_cc Richard Henderson
2015-09-07 17:11 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-09-07 17:17 ` Peter Maydell
2015-09-08 5:12 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless Richard Henderson
2015-09-07 17:31 ` Peter Maydell
2015-09-08 5:18 ` Richard Henderson
2015-09-08 8:19 ` Peter Maydell
2015-09-08 15:20 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-09-07 17:42 ` Peter Maydell
2015-09-08 15:21 ` Richard Henderson
2015-09-02 17:57 ` Richard Henderson [this message]
2015-09-07 17:47 ` [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-09-07 18:00 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-09-07 18:02 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 10/11] target-arm: Recognize ROR Richard Henderson
2015-09-07 18:06 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32 Richard Henderson
2015-09-07 18:11 ` Peter Maydell
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