From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, proljc@gmail.com
Subject: [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit
Date: Wed, 2 Sep 2015 17:17:35 -0700 [thread overview]
Message-ID: <1441239463-18981-10-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1441239463-18981-1-git-send-email-rth@twiddle.net>
True, this is unused so far, but commented out is worse than
actually implemented properly.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-openrisc/int_helper.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c
index f75e1b3..6e12fab 100644
--- a/target-openrisc/int_helper.c
+++ b/target-openrisc/int_helper.c
@@ -25,19 +25,20 @@
target_ulong HELPER(ff1)(target_ulong x)
{
-/*#ifdef TARGET_OPENRISC64
- return x ? ctz64(x) + 1 : 0;
-#else*/
- return x ? ctz32(x) + 1 : 0;
-/*#endif*/
+ if (x == 0) {
+ return 0;
+ } else if (TARGET_LONG_BITS == 64) {
+ return ctz64(x) + 1;
+ } else {
+ return ctz32(x) + 1;
+ }
}
target_ulong HELPER(fl1)(target_ulong x)
{
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- return 64 - clz64(x);
-#else*/
- return 32 - clz32(x);
-/*#endif*/
+ if (TARGET_LONG_BITS == 64) {
+ return 64 - clz64(x);
+ } else {
+ return 32 - clz32(x);
+ }
}
--
2.4.3
next prev parent reply other threads:[~2015-09-03 0:17 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-03 0:17 [Qemu-devel] [PATCH 00/17] target-openrisc improvements Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS Richard Henderson
2015-09-03 14:15 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE Richard Henderson
2015-09-03 14:16 ` Bastian Koppelmann
2015-09-03 14:44 ` Richard Henderson
2015-09-04 13:12 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc Richard Henderson
2015-09-03 14:48 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable Richard Henderson
2015-09-03 15:09 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate Richard Henderson
2015-09-03 16:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags Richard Henderson
2015-09-04 13:05 ` Bastian Koppelmann
2015-09-04 14:29 ` Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2015-09-04 13:33 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers Richard Henderson
2015-09-04 13:58 ` Bastian Koppelmann
2015-09-03 0:17 ` Richard Henderson [this message]
2015-09-04 13:59 ` [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2015-09-04 15:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction Richard Henderson
2015-09-04 15:24 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode Richard Henderson
2015-09-05 21:35 ` Bastian Koppelmann
2015-09-06 20:36 ` Richard Henderson
2015-09-13 8:34 ` Bastian Koppelmann
2015-09-14 17:11 ` Richard Henderson
2015-09-15 7:22 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for " Richard Henderson
2015-09-06 9:30 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2015-09-06 11:38 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd Richard Henderson
2015-09-13 8:21 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception Richard Henderson
2015-09-15 13:02 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa Richard Henderson
2015-09-15 13:04 ` Bastian Koppelmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1441239463-18981-10-git-send-email-rth@twiddle.net \
--to=rth@twiddle.net \
--cc=peter.maydell@linaro.org \
--cc=proljc@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).