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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized CPU affinity handling
Date: Fri,  4 Sep 2015 16:05:56 +0100	[thread overview]
Message-ID: <1441379156-23939-28-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1441379156-23939-1-git-send-email-peter.maydell@linaro.org>

From: Pavel Fedin <p.fedin@samsung.com>

At least with KVM, currently there's no reason why QEMU would not be
capable of handling Aff3 != 0. This commit fixes up FDT creation in such
a case.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Message-id: eef5a86e6d9a313780dbc23b35fcb65df42a3e9e.1441366248.git.p.fedin@samsung.com
[PMM: folded two overlong lines]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 60736c2..91e45e0 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -288,9 +288,32 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
 {
     int cpu;
+    int addr_cells = 1;
+
+    /*
+     * From Documentation/devicetree/bindings/arm/cpus.txt
+     *  On ARM v8 64-bit systems value should be set to 2,
+     *  that corresponds to the MPIDR_EL1 register size.
+     *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
+     *  in the system, #address-cells can be set to 1, since
+     *  MPIDR_EL1[63:32] bits are not used for CPUs
+     *  identification.
+     *
+     *  Here we actually don't know whether our system is 32- or 64-bit one.
+     *  The simplest way to go is to examine affinity IDs of all our CPUs. If
+     *  at least one of them has Aff3 populated, we set #address-cells to 2.
+     */
+    for (cpu = 0; cpu < vbi->smp_cpus; cpu++) {
+        ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
+
+        if (armcpu->mp_affinity & ARM_AFF3_MASK) {
+            addr_cells = 2;
+            break;
+        }
+    }
 
     qemu_fdt_add_subnode(vbi->fdt, "/cpus");
-    qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1);
+    qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells);
     qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
 
     for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
@@ -307,7 +330,14 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
                                         "enable-method", "psci");
         }
 
-        qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", armcpu->mp_affinity);
+        if (addr_cells == 2) {
+            qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg",
+                                 armcpu->mp_affinity);
+        } else {
+            qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg",
+                                  armcpu->mp_affinity);
+        }
+
         g_free(nodename);
     }
 }
-- 
1.9.1

  parent reply	other threads:[~2015-09-04 15:06 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 04/27] gdbstub: Implement gdb_do_syscallv() Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 06/27] include/exec/softmmu-semi.h: Add support for 64-bit values Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31 Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25 Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform Peter Maydell
2015-09-27 19:48   ` Peter Crosthwaite
2015-09-27 19:52     ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 24/27] i.MX: Add qtest support for I2C device emulator Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling Peter Maydell
2015-09-04 15:05 ` Peter Maydell [this message]
2015-09-07  9:40 ` [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell

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