From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7Z-0002Yi-0p for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZM7X-00083I-SV for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:48 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35050) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7X-0007xj-KU for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:47 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZZM7I-0001i6-Hw for qemu-devel@nongnu.org; Tue, 08 Sep 2015 17:51:32 +0100 From: Peter Maydell Date: Tue, 8 Sep 2015 17:51:21 +0100 Message-Id: <1441731092-6513-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> References: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org If the A9 and A15 CPUs which we're creating the peripherals for have TrustZone (EL3) enabled, then also enable it in the GIC we create. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 1441383782-24378-5-git-send-email-peter.maydell@linaro.org --- hw/cpu/a15mpcore.c | 13 +++++++++++++ hw/cpu/a9mpcore.c | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 58ac02e..4ef8db1 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -52,10 +52,23 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) SysBusDevice *busdev; int i; Error *err = NULL; + bool has_el3; + Object *cpuobj; gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + + if (!kvm_irqchip_in_kernel()) { + /* Make the GIC's TZ support match the CPUs. We assume that + * either all the CPUs have TZ, or none do. + */ + cpuobj = OBJECT(qemu_get_cpu(0)); + has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && + object_property_get_bool(cpuobj, "has_el3", &error_abort); + qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + } + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c09358c..7046246 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -49,6 +49,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) *wdtbusdev; Error *err = NULL; int i; + bool has_el3; + Object *cpuobj; scudev = DEVICE(&s->scu); qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); @@ -62,6 +64,15 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + + /* Make the GIC's TZ support match the CPUs. We assume that + * either all the CPUs have TZ, or none do. + */ + cpuobj = OBJECT(qemu_get_cpu(0)); + has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && + object_property_get_bool(cpuobj, "has_el3", &error_abort); + qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); -- 1.9.1