From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7V-0002TV-RC for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZM7U-0007s6-2a for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:45 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35049) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7T-0007b2-SY for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:44 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZZM7I-0001iQ-OM for qemu-devel@nongnu.org; Tue, 08 Sep 2015 17:51:32 +0100 From: Peter Maydell Date: Tue, 8 Sep 2015 17:51:26 +0100 Message-Id: <1441731092-6513-15-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> References: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 1441311266-8644-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 040bc70..38a05e1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2975,16 +2975,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, - .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 4, + .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, - .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 5, + .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, - .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6, + .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, - .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 7, + .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, -- 1.9.1