From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7U-0002TA-8l for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZM7T-0007r7-Gm for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:44 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35049) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7T-0007b2-A4 for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:43 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZZM7I-0001iY-Qs for qemu-devel@nongnu.org; Tue, 08 Sep 2015 17:51:32 +0100 From: Peter Maydell Date: Tue, 8 Sep 2015 17:51:28 +0100 Message-Id: <1441731092-6513-17-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> References: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Alistair Francis Bit 15 of the PHY Specific Status Register is reserved and should remain 0. Fix the reset value to ensure that the 15th bit is not set. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: c795069e49040ff770fe2ece19dfe1791b729e22.1441316450.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 494a346..1127223 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s) s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; - s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; + s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; s->phy_regs[PHY_REG_LED] = 0x4100; s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; -- 1.9.1