From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header
Date: Tue, 8 Sep 2015 17:51:29 +0100 [thread overview]
Message-ID: <1441731092-6513-18-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org>
From: Alistair Francis <alistair.francis@xilinx.com>
Pull the AHCI state structure out into the header. This allows
other containers to access the struct. This is required to add
the device to modern SoC containers.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ide/ahci.c | 13 -------------
hw/ide/ahci.h | 14 ++++++++++++++
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 48749c1..02d85fa 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -25,7 +25,6 @@
#include <hw/pci/msi.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
-#include <hw/sysbus.h>
#include "qemu/error-report.h"
#include "sysemu/block-backend.h"
@@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
},
};
-#define TYPE_SYSBUS_AHCI "sysbus-ahci"
-#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
-
-typedef struct SysbusAHCIState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- AHCIState ahci;
- uint32_t num_ports;
-} SysbusAHCIState;
-
static const VMStateDescription vmstate_sysbus_ahci = {
.name = "sysbus-ahci",
.fields = (VMStateField[]) {
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 79a463d..c055d6b 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -24,6 +24,8 @@
#ifndef HW_IDE_AHCI_H
#define HW_IDE_AHCI_H
+#include <hw/sysbus.h>
+
#define AHCI_MEM_BAR_SIZE 0x1000
#define AHCI_MAX_PORTS 32
#define AHCI_MAX_SG 168 /* hardware max is 64K */
@@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
+#define TYPE_SYSBUS_AHCI "sysbus-ahci"
+#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
+
+typedef struct SysbusAHCIState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ AHCIState ahci;
+ uint32_t num_ports;
+} SysbusAHCIState;
+
#endif /* HW_IDE_AHCI_H */
--
1.9.1
next prev parent reply other threads:[~2015-09-08 16:51 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-08 16:51 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 03/20] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS " Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 13/20] target-arm: Log the target EL when taking exceptions Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1 Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value Peter Maydell
2015-09-08 16:51 ` Peter Maydell [this message]
2015-09-08 16:51 ` [Qemu-devel] [PULL 18/20] ahci.c: Don't assume AHCIState's parent is AHCIPCIState Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 20/20] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP Peter Maydell
2015-09-08 19:08 ` [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
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