From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7X-0002Wa-Nl for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZM7R-0007lO-Pa for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:47 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35049) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZM7R-0007b2-Id for qemu-devel@nongnu.org; Tue, 08 Sep 2015 12:51:41 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZZM7I-0001ha-7F for qemu-devel@nongnu.org; Tue, 08 Sep 2015 17:51:32 +0100 From: Peter Maydell Date: Tue, 8 Sep 2015 17:51:13 +0100 Message-Id: <1441731092-6513-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> References: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Change the implementation of the Interrupt Control and State Register in the v7M NVIC to not use the running_irq and last_active internal state fields in the GIC. These fields don't correspond to state in a real GIC and will be removed soon. The changes to the ICSR are: * the VECTACTIVE field is documented as identical to the IPSR[8:0] field, so implement it that way * implement RETTOBASE via looking at the active state bits Signed-off-by: Peter Maydell Message-id: 1438089748-5528-2-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e13b729..3ec8408 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -185,26 +185,25 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) return cpu->midr; case 0xd04: /* Interrupt Control State. */ /* VECTACTIVE */ - val = s->gic.running_irq[0]; + cpu = ARM_CPU(current_cpu); + val = cpu->env.v7m.exception; if (val == 1023) { val = 0; } else if (val >= 32) { val -= 16; } - /* RETTOBASE */ - if (s->gic.running_irq[0] == 1023 - || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) { - val |= (1 << 11); - } /* VECTPENDING */ if (s->gic.current_pending[0] != 1023) val |= (s->gic.current_pending[0] << 12); - /* ISRPENDING */ + /* ISRPENDING and RETTOBASE */ for (irq = 32; irq < s->num_irq; irq++) { if (s->gic.irq_state[irq].pending) { val |= (1 << 22); break; } + if (irq != cpu->env.v7m.exception && s->gic.irq_state[irq].active) { + val |= (1 << 11); + } } /* PENDSTSET */ if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending) -- 1.9.1