From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 20/20] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
Date: Tue, 8 Sep 2015 17:51:32 +0100 [thread overview]
Message-ID: <1441731092-6513-21-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1441731092-6513-1-git-send-email-peter.maydell@linaro.org>
From: Alistair Francis <alistair.francis@xilinx.com>
Connect the Sysbus AHCI device to ZynqMP.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
[PMM: removed unnecessary brackets in error_propagate call]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-zynqmp.c | 18 ++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 6756c74..2955f3b 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -28,6 +28,10 @@
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
+#define SATA_INTR 133
+#define SATA_ADDR 0xFD0C0000
+#define SATA_NUM_PORTS 2
+
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
@@ -90,6 +94,9 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
}
+
+ object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
+ qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -240,6 +247,17 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
gic_spi[uart_intr[i]]);
}
+
+ object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
}
static Property xlnx_zynqmp_props[] = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 6ccb57b..97622ec 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,8 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/ide/pci.h"
+#include "hw/ide/ahci.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -60,6 +62,7 @@ typedef struct XlnxZynqMPState {
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+ SysbusAHCIState sata;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
--
1.9.1
next prev parent reply other threads:[~2015-09-08 16:51 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-08 16:51 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 03/20] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS " Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 13/20] target-arm: Log the target EL when taking exceptions Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1 Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 18/20] ahci.c: Don't assume AHCIState's parent is AHCIPCIState Peter Maydell
2015-09-08 16:51 ` [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort Peter Maydell
2015-09-08 16:51 ` Peter Maydell [this message]
2015-09-08 19:08 ` [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
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