From: Benjamin Herrenschmidt <benh@au1.ibm.com>
To: Anton Blanchard <anton@samba.org>, agraf@suse.de
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] target-ppc: Fix SRR0 when taking unaligned exceptions
Date: Wed, 09 Sep 2015 08:21:36 +1000 [thread overview]
Message-ID: <1441750896.2767.15.camel@au1.ibm.com> (raw)
In-Reply-To: <20150702144406.40bce749@kryten>
On Thu, 2015-07-02 at 14:44 +1000, Anton Blanchard wrote:
> We are setting SRR0 to the instruction before the one causing the
> unaligned exception. A quick testcase:
>
../..
> p_helper.c b/target-ppc/excp_helper.c
> index b803475..4250106 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -200,7 +200,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu,
> int excp_model, int excp)
> /* Get rS/rD and rA from faulting opcode */
> env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4))
> & 0x03FF0000) >> 16;.
You need to also fix the above to use env->nip instead of env->nip - 4
when generating DSISR
> - goto store_current;
> + goto store_next;
> case POWERPC_EXCP_PROGRAM: /* Program exception
> */
> switch (env->error_code & ~0xF) {
> case POWERPC_EXCP_FP:
prev parent reply other threads:[~2015-09-08 22:22 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-02 4:44 [Qemu-devel] target-ppc: Fix SRR0 when taking unaligned exceptions Anton Blanchard
2015-08-26 9:44 ` Alexander Graf
2015-09-08 22:21 ` Benjamin Herrenschmidt [this message]
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