From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZaxb-000547-AV for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZaxa-0001r6-EX for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:31 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:32990) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZaxa-0001r2-8L for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:30 -0400 Received: by pacex6 with SMTP id ex6so4005855pac.0 for ; Wed, 09 Sep 2015 01:42:29 -0700 (PDT) From: Tushar Jagad Date: Wed, 9 Sep 2015 08:42:10 +0000 Message-Id: <1441788132-6286-2-git-send-email-tushar.jagad@linaro.org> In-Reply-To: <1441788132-6286-1-git-send-email-tushar.jagad@linaro.org> References: <1441788132-6286-1-git-send-email-tushar.jagad@linaro.org> Subject: [Qemu-devel] [PATCH RFC 1/3] linux-headers: sync'd kernel headers for arm/arm64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, patches@apm.com, tushar.jagad@linaro.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Sync arm/arm64 headers for bringing in support for cross cpu. Signed-off-by: Tushar Jagad --- linux-headers/asm-arm64/kvm.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index c8abf25..94d1fc9 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -88,6 +88,13 @@ struct kvm_regs { #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ +#define KVM_ARM_VCPU_NUM_BPTS 3 /* Number of breakpoints supported */ +#define KVM_ARM_VCPU_NUM_WPTS 7 /* Number of watchpoints supported */ + +#define KVM_ARM_VCPU_BPTS_FEATURES_IDX 0 +#define KVM_ARM_VCPU_WPTS_FEATURES_IDX 0 +#define KVM_ARM_VCPU_BPTS_MASK 0x00000078 +#define KVM_ARM_VCPU_WPTS_MASK 0x00000780 struct kvm_vcpu_init { __u32 target; @@ -193,7 +200,9 @@ struct kvm_arch_memory_slot { * and only here to provide source code level compatibility with older * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. */ +#ifndef __KERNEL__ #define KVM_ARM_IRQ_GIC_MAX 127 +#endif /* One single KVM irqchip, ie. the VGIC */ #define KVM_NR_IRQCHIPS 1 -- 2.4.3