From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 2/2] target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl()
Date: Mon, 14 Sep 2015 13:45:54 +0100 [thread overview]
Message-ID: <1442234754-15692-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1442234754-15692-1-git-send-email-leon.alrae@imgtec.com>
Remove misleading gen_mfc0_load64() which actually loads 32 or 64 bits
depending whether MIPS32 or MIPS64 and also replace the pair of
tcg_gen_ld_tl() + tcg_gen_ext32s_tl() with single tcg_gen_ld32s_tl().
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate.c | 43 +++++++++++++++++--------------------------
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8bb45df..7fb7c01 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4750,12 +4750,6 @@ static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
tcg_temp_free_i32(t0);
}
-static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
-{
- tcg_gen_ld_tl(arg, cpu_env, off);
- tcg_gen_ext32s_tl(arg, arg);
-}
-
static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
{
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -4972,17 +4966,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 4:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
+ tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
+ tcg_gen_ld32s_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+ tcg_gen_ld32s_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -5078,8 +5074,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
rn = "Context";
break;
case 1:
@@ -5161,8 +5156,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_BadVAddr));
rn = "BadVAddr";
break;
case 1:
@@ -5203,8 +5198,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
rn = "EntryHi";
break;
default:
@@ -5260,8 +5254,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -5357,8 +5350,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_XContext));
rn = "XContext";
break;
#endif
@@ -5412,8 +5405,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -5520,8 +5512,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -5537,9 +5529,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 2 ... 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_ld_tl(arg, cpu_env,
- offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
- tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_ld32s_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
rn = "KScratch";
break;
default:
--
2.1.0
next prev parent reply other threads:[~2015-09-14 12:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-14 12:45 [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0 Leon Alrae
2015-09-14 12:45 ` [Qemu-devel] [PATCH 1/2] target-mips: correct MTC0 instruction on MIPS64 Leon Alrae
2015-09-14 12:45 ` Leon Alrae [this message]
2015-09-16 18:14 ` [Qemu-devel] [PATCH 2/2] target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl() Richard Henderson
2015-09-16 19:00 ` Leon Alrae
2015-09-16 4:46 ` [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0 Aurelien Jarno
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